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/*==========================================================================*/
/* Sail */
/* */
/* Sail and the Sail architecture models here, comprising all files and */
/* directories except the ASL-derived Sail code in the aarch64 directory, */
/* are subject to the BSD two-clause licence below. */
/* */
/* The ASL derived parts of the ARMv8.3 specification in */
/* aarch64/no_vector and aarch64/full are copyright ARM Ltd. */
/* */
/* Copyright (c) 2013-2024 */
/* Kathyrn Gray */
/* Shaked Flur */
/* Stephen Kell */
/* Gabriel Kerneis */
/* Robert Norton-Wright */
/* Christopher Pulte */
/* Peter Sewell */
/* Alasdair Armstrong */
/* Brian Campbell */
/* Thomas Bauereiss */
/* Anthony Fox */
/* Jon French */
/* Dominic Mulligan */
/* Stephen Kell */
/* Mark Wassell */
/* Alastair Reid (Arm Ltd) */
/* */
/* All rights reserved. */
/* */
/* This work was partially supported by EPSRC grant EP/K008528/1 <a */
/* href="http://www.cl.cam.ac.uk/users/pes20/rems">REMS: Rigorous */
/* Engineering for Mainstream Systems</a>, an ARM iCASE award, EPSRC IAA */
/* KTF funding, and donations from Arm. This project has received */
/* funding from the European Research Council (ERC) under the European */
/* Union’s Horizon 2020 research and innovation programme (grant */
/* agreement No 789108, ELVER). */
/* */
/* This software was developed by SRI International and the University of */
/* Cambridge Computer Laboratory (Department of Computer Science and */
/* Technology) under DARPA/AFRL contracts FA8650-18-C-7809 ("CIFV") */
/* and FA8750-10-C-0237 ("CTSRD"). */
/* */
/* SPDX-License-Identifier: BSD-2-Clause */
/*==========================================================================*/
$sail_internal
$ifndef _CONCURRENCY_INTERFACE_SYSREG
$define _CONCURRENCY_INTERFACE_SYSREG
$include <concurrency_interface/common.sail>
/* An experimental interface for reporting explicit system register
accesses to concurrency models. The id doesn't need to match the
actual model register used - it could be (for example) the
identifier used in the instruction for the access.
At the moment there is some support for this in the Coq backend,
in addition to the plain emulation implementation below. */
outcome sail_sys_reg_write : forall 'a. ('id, register('a), 'a) -> unit
with
'id : Type
= {
impl emulator_or_isla(_id, reg, value) = *reg = value
}
outcome sail_sys_reg_read : forall 'a. ('id, register('a)) -> 'a
with
'id : Type
= {
impl emulator_or_isla(_id, reg) = *reg
}
$endif
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