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import Out.Sail.Sail
import Out.Sail.BitVec
open PreSail
set_option maxHeartbeats 1_000_000_000
set_option maxRecDepth 1_000_000
set_option linter.unusedVariables false
set_option match.ignoreUnusedAlts true
open Sail
abbrev bits k_n := (BitVec k_n)
/-- Type quantifiers: k_a : Type -/
inductive option (k_a : Type) where
| Some (_ : k_a)
| None (_ : Unit)
deriving Inhabited, BEq, Repr
inductive word_width where | BYTE | HALF | WORD | DOUBLE
deriving BEq, Inhabited, Repr
abbrev Register := PEmpty
abbrev RegisterType : Register -> Type := PEmpty.elim
abbrev exception := Unit
abbrev SailM := PreSailM RegisterType trivialChoiceSource exception
XXXXXXXXX
import Out.Sail.Sail
import Out.Sail.BitVec
import Out.Sail.IntRange
import Out.Defs
import Out.Specialization
import Out.FakeReal
set_option maxHeartbeats 1_000_000_000
set_option maxRecDepth 1_000_000
set_option linter.unusedVariables false
set_option match.ignoreUnusedAlts true
open Sail
namespace Out.Functions
open word_width
open option
/-- Type quantifiers: k_ex777# : Bool, k_ex776# : Bool -/
def neq_bool (x : Bool) (y : Bool) : Bool :=
(! (x == y))
/-- Type quantifiers: x : Int -/
def __id (x : Int) : Int :=
x
/-- Type quantifiers: n : Int, m : Int -/
def _shl_int_general (m : Int) (n : Int) : Int :=
bif (n ≥b 0)
then (Int.shiftl m n)
else (Int.shiftr m (Neg.neg n))
/-- Type quantifiers: n : Int, m : Int -/
def _shr_int_general (m : Int) (n : Int) : Int :=
bif (n ≥b 0)
then (Int.shiftr m n)
else (Int.shiftl m (Neg.neg n))
/-- Type quantifiers: m : Int, n : Int -/
def fdiv_int (n : Int) (m : Int) : Int :=
bif ((n <b 0) && (m >b 0))
then ((Int.tdiv (n +i 1) m) -i 1)
else
(bif ((n >b 0) && (m <b 0))
then ((Int.tdiv (n -i 1) m) -i 1)
else (Int.tdiv n m))
/-- Type quantifiers: m : Int, n : Int -/
def fmod_int (n : Int) (m : Int) : Int :=
(n -i (m *i (fdiv_int n m)))
/-- Type quantifiers: len : Nat, k_v : Nat, len ≥ 0 ∧ k_v ≥ 0 -/
def sail_mask (len : Nat) (v : (BitVec k_v)) : (BitVec len) :=
bif (len ≤b (Sail.BitVec.length v))
then (Sail.BitVec.truncate v len)
else (Sail.BitVec.zeroExtend v len)
/-- Type quantifiers: n : Nat, n ≥ 0 -/
def sail_ones (n : Nat) : (BitVec n) :=
(Complement.complement (BitVec.zero n))
/-- Type quantifiers: l : Int, i : Int, n : Nat, n ≥ 0 -/
def slice_mask {n : _} (i : Int) (l : Int) : (BitVec n) :=
bif (l ≥b n)
then ((sail_ones n) <<< i)
else
(let one : (BitVec n) := (sail_mask n (0b1 : (BitVec 1)))
(((one <<< l) - one) <<< i))
/-- Type quantifiers: n : Nat, n > 0 -/
def to_bytes_le {n : _} (b : (BitVec (8 * n))) : (Vector (BitVec 8) n) := Id.run do
let res := (vectorInit (BitVec.zero 8))
let loop_i_lower := 0
let loop_i_upper := (n -i 1)
let mut loop_vars := res
for i in [loop_i_lower:loop_i_upper:1]i do
let res := loop_vars
loop_vars := (vectorUpdate res i (Sail.BitVec.extractLsb b ((8 *i i) +i 7) (8 *i i)))
(pure loop_vars)
/-- Type quantifiers: n : Nat, n > 0 -/
def from_bytes_le {n : _} (v : (Vector (BitVec 8) n)) : (BitVec (8 * n)) := Id.run do
let res := (BitVec.zero (8 *i n))
let loop_i_lower := 0
let loop_i_upper := (n -i 1)
let mut loop_vars := res
for i in [loop_i_lower:loop_i_upper:1]i do
let res := loop_vars
loop_vars := (Sail.BitVec.updateSubrange res ((8 *i i) +i 7) (8 *i i) (GetElem?.getElem! v i))
(pure loop_vars)
/-- Type quantifiers: k_a : Type -/
def is_none (opt : (Option k_a)) : Bool :=
match opt with
| .some _ => false
| none => true
/-- Type quantifiers: k_a : Type -/
def is_some (opt : (Option k_a)) : Bool :=
match opt with
| .some _ => true
| none => false
/-- Type quantifiers: k_n : Int -/
def concat_str_bits (str : String) (x : (BitVec k_n)) : String :=
(HAppend.hAppend str (BitVec.toFormatted x))
/-- Type quantifiers: x : Int -/
def concat_str_dec (str : String) (x : Int) : String :=
(HAppend.hAppend str (Int.repr x))
def undefined_word_width (_ : Unit) : SailM word_width := do
(internal_pick [BYTE, HALF, WORD, DOUBLE])
/-- Type quantifiers: arg_ : Nat, 0 ≤ arg_ ∧ arg_ ≤ 3 -/
def word_width_of_num (arg_ : Nat) : word_width :=
match arg_ with
| 0 => BYTE
| 1 => HALF
| 2 => WORD
| _ => DOUBLE
def num_of_word_width (arg_ : word_width) : Int :=
match arg_ with
| BYTE => 0
| HALF => 1
| WORD => 2
| DOUBLE => 3
def size_bits_forwards (arg_ : word_width) : (BitVec 2) :=
match arg_ with
| BYTE => (0b00 : (BitVec 2))
| HALF => (0b01 : (BitVec 2))
| WORD => (0b10 : (BitVec 2))
| DOUBLE => (0b11 : (BitVec 2))
def size_bits_backwards (arg_ : (BitVec 2)) : word_width :=
match_bv arg_ with
| 00 => BYTE
| 01 => HALF
| 10 => WORD
| _ => DOUBLE
def size_bits_forwards_matches (arg_ : word_width) : Bool :=
match arg_ with
| BYTE => true
| HALF => true
| WORD => true
| DOUBLE => true
| _ => false
def size_bits_backwards_matches (arg_ : (BitVec 2)) : Bool :=
match_bv arg_ with
| 00 => true
| 01 => true
| 10 => true
| 11 => true
| _ => false
def size_bits2_forwards (arg_ : word_width) : (BitVec 2) :=
match arg_ with
| BYTE => (0b00 : (BitVec 2))
| HALF => (0b01 : (BitVec 2))
| WORD => (0b10 : (BitVec 2))
| DOUBLE => (0b11 : (BitVec 2))
def size_bits2_backwards (arg_ : (BitVec 2)) : word_width :=
match_bv arg_ with
| 00 => BYTE
| 01 => HALF
| 10 => WORD
| _ => DOUBLE
def size_bits2_forwards_matches (arg_ : word_width) : Bool :=
match arg_ with
| BYTE => true
| HALF => true
| WORD => true
| DOUBLE => true
| _ => false
def size_bits2_backwards_matches (arg_ : (BitVec 2)) : Bool :=
match_bv arg_ with
| 00 => true
| 01 => true
| 10 => true
| 11 => true
| _ => false
def size_bits3_forwards (arg_ : word_width) : (BitVec 2) :=
match arg_ with
| BYTE => (0b00 : (BitVec 2))
| HALF => (0b01 : (BitVec 2))
| WORD => (0b10 : (BitVec 2))
| DOUBLE => (0b11 : (BitVec 2))
def size_bits3_backwards (arg_ : (BitVec 2)) : word_width :=
match_bv arg_ with
| 00 => BYTE
| 01 => HALF
| 10 => WORD
| _ => DOUBLE
def size_bits3_forwards_matches (arg_ : word_width) : Bool :=
match arg_ with
| BYTE => true
| HALF => true
| WORD => true
| DOUBLE => true
| _ => false
def size_bits3_backwards_matches (arg_ : (BitVec 2)) : Bool :=
match_bv arg_ with
| 00 => true
| 01 => true
| 10 => true
| 11 => true
| _ => false
def initialize_registers (_ : Unit) : Unit :=
()
def sail_model_init (x_0 : Unit) : Unit :=
(initialize_registers ())
end Out.Functions
|
