1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
|
$include <flow.sail>
enum boolean = {FALSE, TRUE}
enum signal = {LOW, HIGH}
enum __RetCode = {
__RC_OK,
__RC_UNDEFINED,
__RC_UNPREDICTABLE,
__RC_SEE,
__RC_IMPLEMENTATION_DEFINED,
__RC_SUBARCHITECTURE_DEFINED,
__RC_EXCEPTION_TAKEN,
__RC_ASSERT_FAILED,
__RC_UNMATCHED_CASE
}
type TUBE_Type = vector(32, inc, bit)
type ScheduleIRQ_Type = vector(32, inc, bit)
type ClearIRQ_Type = vector(32, inc, bit)
type ScheduleFIQ_Type = vector(32, inc, bit)
type ClearFIQ_Type = vector(32, inc, bit)
type TargetCPU_Type = vector(32, inc, bit)
type AbortRgn64Lo1_Type = vector(32, inc, bit)
type AbortRgn64Lo1_Hi_Type = vector(32, inc, bit)
type AbortRgn64Hi1_Type = vector(32, inc, bit)
type AbortRgn64Hi1_Hi_Type = vector(32, inc, bit)
type AbortRgn64Lo2_Type = vector(32, inc, bit)
type AbortRgn64Lo2_Hi_Type = vector(32, inc, bit)
type AbortRgn64Hi2_Type = vector(32, inc, bit)
type AbortRgn64Hi2_Hi_Type = vector(32, inc, bit)
type AXIAbortCtl_Type = vector(32, inc, bit)
type GTE_API_Type = vector(32, inc, bit)
type GTE_API_PARAM_Type = vector(32, inc, bit)
type GTE_API_STATUS_Type = vector(32, inc, bit)
type PPURBAR_Type = vector(32, inc, bit)
type PPURSER_Type = vector(32, inc, bit)
type PPURACR_Type = vector(32, inc, bit)
type GTE_API_STATUS_64_Type = vector(32, inc, bit)
type GTE_API_STATUS_64_HI_Type = vector(32, inc, bit)
type GTE_API_PARAM_64_Type = vector(32, inc, bit)
type GTE_API_PARAM_64_HI_Type = vector(32, inc, bit)
enum MemAtomicOp = {
MemAtomicOp_ADD,
MemAtomicOp_BIC,
MemAtomicOp_EOR,
MemAtomicOp_ORR,
MemAtomicOp_SMAX,
MemAtomicOp_SMIN,
MemAtomicOp_UMAX,
MemAtomicOp_UMIN,
MemAtomicOp_SWP
}
type SCRType = vector(32, inc, bit)
type SCTLRType = vector(32, inc, bit)
type MAIRType = vector(64, inc, bit)
type ESRType = vector(32, inc, bit)
type FPCRType = vector(32, inc, bit)
type FPSRType = vector(32, inc, bit)
type FPSCRType = vector(32, inc, bit)
type CPSRType = vector(32, inc, bit)
type APSRType = vector(32, inc, bit)
type ITSTATEType = vector(8, inc, bit)
type CPACRType = vector(32, inc, bit)
type CNTKCTLType = vector(32, inc, bit)
enum GTEParamType = {GTEParam_WORD, GTEParam_LIST, GTEParam_EOACCESS}
type GTE_PPU_SizeEn_Type = vector(32, inc, bit)
type GTEExtObsAccess_Type = vector(16, inc, bit)
type GTEASAccess_Type = vector(32, inc, bit)
type GTEASRecordedAccess_Type = vector(32, inc, bit)
enum AccType = {
AccType_NORMAL,
AccType_VEC,
AccType_STREAM,
AccType_VECSTREAM,
AccType_ATOMIC,
AccType_ORDERED,
AccType_UNPRIV,
AccType_IFETCH,
AccType_PTW,
AccType_DC,
AccType_IC,
AccType_DCZVA,
AccType_AT
}
enum MemType = {MemType_Normal, MemType_Device}
enum DeviceType = {
DeviceType_GRE,
DeviceType_nGRE,
DeviceType_nGnRE,
DeviceType_nGnRnE
}
struct MemAttrHints = {
attrs : vector(2, inc, bit),
hints : vector(2, inc, bit),
transient : bool
}
struct MemoryAttributes = {
typ : MemType,
device : DeviceType,
inner : MemAttrHints,
outer : MemAttrHints,
shareable : bool,
outershareable : bool
}
|
