File: mapping_rreg.sail

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sail-ocaml 0.19.1%2Bdfsg5-1
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default Order dec

$include <prelude.sail>

register enabled : bits(1)

union ast = {
  I: bits(1)
}

val encdec : ast <-> bits(2) effect {rreg}

scattered mapping encdec

mapping clause encdec = I(imm) if enabled == 0b0 <-> 0b0 @ imm if enabled == 0b0

end encdec