1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
|
#! /usr/bin/env python
###############################################################################
#
# simulavr - A simulator for the Atmel AVR family of microcontrollers.
# Copyright (C) 2001, 2002 Theodore A. Roth
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 2 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
#
###############################################################################
#
# $Id: test_AND.py,v 1.2 2002/02/23 05:29:18 troth Exp $
#
"""Test the AND opcode.
"""
import base_test
from registers import Reg, SREG
class AND_TestFail(base_test.TestFail): pass
class base_AND(base_test.opcode_test):
"""Generic test case for testing AND opcode.
AND - Logical AND
opcode is '0010 00rd dddd rrrr' where r and d are registers (d is destination).
Only registers PC, Rd and SREG should be changed.
"""
def setup(self):
# Set SREG to have only V set (opcode should clear it)
self.setup_regs[Reg.SREG] = 1 << SREG.V
# Set the register values
self.setup_regs[self.Rd] = self.Vd
self.setup_regs[self.Rr] = self.Vr
# Return the raw opcode
return 0x2000 | (self.Rd << 4) | ((self.Rr & 0x10) << 5) | (self.Rr & 0xf)
def analyze_results(self):
self.reg_changed.extend( [self.Rd, Reg.SREG] )
# check that result is correct
expect = ((self.Vd & self.Vr) & 0xff)
got = self.anal_regs[self.Rd]
if expect != got:
self.fail('AND r%02d, r%02d: 0x%02x & 0x%02x = (expect=%02x, got=%02x)' % (
self.Rd, self.Rr, self.Vd, self.Vr, expect, got))
expect_sreg = 0
# calculate what we expect sreg to be (I, T, H, V and C should be zero)
V = 0
N = ((expect & 0x80) != 0)
expect_sreg += N << SREG.N
expect_sreg += (N ^ V) << SREG.S
expect_sreg += (expect == 0) << SREG.Z
got_sreg = self.anal_regs[Reg.SREG]
if expect_sreg != got_sreg:
self.fail('AND r%02d, r%02d: 0x%02x + 0x%02x -> SREG (expect=%02x, got=%02x)' % (
self.Rd, self.Rr, self.Vd, self.Vr, expect_sreg, got_sreg))
#
# Template code for test case.
# The fail method will raise a test specific exception.
#
template = """
class AND_rd%02d_vd%02x_rr%02d_vr%02x_TestFail(AND_TestFail): pass
class test_AND_rd%02d_vd%02x_rr%02d_vr%02x(base_AND):
Rd = %d
Vd = 0x%x
Rr = %d
Vr = 0x%x
def fail(self,s):
raise AND_rd%02d_vd%02x_rr%02d_vr%02x_TestFail, s
"""
#
# Define a list of test values such that we test all the cases of SREG bits being set.
#
vals = (
( 0x00, 0x00 ),
( 0xff, 0x00 ),
( 0xfe, 0x01 ),
( 0x0f, 0x00 ),
( 0x0f, 0xf0 ),
( 0x01, 0x02 ),
( 0x80, 0x80 )
)
#
# automagically generate the test_AND_rdNN_vdXX_rrNN_vrXX class definitions.
# For these, we don't want Rd=Rr as that is a special case handled below.
#
code = ''
for d in range(0,32,4):
for r in range(1,32,4):
for vd,vr in vals:
args = (d,vd,r,vr)*4
code += template % args
#
# This is effectively a TST operation (Rd == Rr)
#
for d in range(0,32,4):
for vd,vr in vals:
args = (d,vd,d,vd)*4
code += template % args
exec code
|
