File: README

package info (click to toggle)
simulavr 1.0.0%2Bgit20160221.e53413b-1
  • links: PTS
  • area: main
  • in suites: buster
  • size: 5,748 kB
  • sloc: cpp: 35,491; python: 6,991; ansic: 3,567; makefile: 1,072; sh: 653; asm: 414; tcl: 320
file content (21 lines) | stat: -rw-r--r-- 360 bytes parent folder | download | duplicates (2) 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
 
This directory contains some examples of how one can use
the VERILOG simulavrxx interface. Just call

> make example

and after that, use 

> make <file>.run

and then

> make <file>.view

with the base name one of the example files (such as baretest.v ->
make baretest.view), to view the results in gtkwave.

Example:

make example
make vst.run
make vst.view