File: portio.py

package info (click to toggle)
simulavr 1.0.0%2Bgit20160221.e53413b-1
  • links: PTS
  • area: main
  • in suites: buster
  • size: 5,748 kB
  • sloc: cpp: 35,491; python: 6,991; ansic: 3,567; makefile: 1,072; sh: 653; asm: 414; tcl: 320
file content (307 lines) | stat: -rw-r--r-- 16,186 bytes parent folder | download | duplicates (2)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
#from types import IntType, FloatType

from simtestutil import PyTestCase, PyTestLoader
import pysimulavr

#class XPin(pysimulavr.Pin):
  
#  def SetInState(self, pin):
#    pysimulavr.Pin.SetInState(self, pin)
#    self.__inState = pin.toChar()
    
#  @property
#  def inState(self): return self.__inState

class TestCase_1(PyTestCase):
  
  """
  This testcase test a regular port without any outer connections, port has feature pin toggle
  """

  def setUp(self):
    # create a avr core, type isn't important
    self.core = pysimulavr.AvrFactory.instance().makeDevice("atmega16")
    # create port with 4 bit and pin toggle feature
    self.port = pysimulavr.HWPort(self.core, "port", True, 4)

  def tearDown(self):
    del self.port
    del self.core

  def test_00(self):
    """check port initial state after reset"""
    self.assertTrue(self.port.GetPortString() == "tttt", "all output pins in tristate")
    self.assertTrue(self.port.GetPort() == 0, "read port register == 0")
    self.assertTrue(self.port.GetPin() == 0xf, "read pin register == 0xf")
    self.assertTrue(self.port.GetDdr() == 0, "read ddr register == 0")
    
  def test_01(self):
    """check, if set ddr work"""
    self.assertTrue(self.port.GetPortString() == "tttt", "all output pins in tristate")
    self.port.SetDdr(0xa) # bit 3 and 1 are output
    self.assertTrue(self.port.GetPort() == 0, "read port register == 0")
    self.assertTrue(self.port.GetPin() == 0x5, "read pin register == 0x5")
    self.assertTrue(self.port.GetDdr() == 0xa, "read ddr register == 0xa")
    self.assertTrue(self.port.GetPortString() == "LtLt", "output pins 3 and 1 to low")
    self.port.SetPort(0xa) # set bits 3 and 1 to high
    self.assertTrue(self.port.GetPort() == 0xa, "read port register == 0xa")
    self.assertTrue(self.port.GetPin() == 0xf, "read pin register == 0xf")
    self.assertTrue(self.port.GetDdr() == 0xa, "read ddr register == 0xa")
    self.assertTrue(self.port.GetPortString() == "HtHt", "output pins 3 and 1 to high")
    self.port.SetDdr(0) # all bits are inputs
    self.assertTrue(self.port.GetPort() == 0xa, "read port register == 0xa")
    self.assertTrue(self.port.GetPin() == 0xf, "read pin register == 0xf")
    self.assertTrue(self.port.GetDdr() == 0, "read ddr register == 0")
    self.assertTrue(self.port.GetPortString() == "htht", "output pins 3 and 1 have pullup")
    self.port.SetPort(0) # port = 0
    self.assertTrue(self.port.GetPort() == 0, "read port register == 0")
    self.assertTrue(self.port.GetPin() == 0xf, "read pin register == 0xf")
    self.assertTrue(self.port.GetPortString() == "tttt", "all output pins in tristate again")

  def test_02(self):
    """check, if pin toggle works"""
    self.assertTrue(self.port.GetPortString() == "tttt", "all output pins in tristate")
    self.port.SetDdr(0x1) # bit 0 is output
    self.assertTrue(self.port.GetPort() == 0, "read port register == 0")
    self.assertTrue(self.port.GetPin() == 0xe, "read pin register == 0xe")
    self.assertTrue(self.port.GetDdr() == 0x1, "read ddr register == 0x1")
    self.assertTrue(self.port.GetPortString() == "tttL", "bit 0 is low")
    self.port.SetPin(0x1)
    self.assertTrue(self.port.GetPort() == 0x1, "read port register == 0x1")
    self.assertTrue(self.port.GetPin() == 0xf, "read pin register == 0xf")
    self.assertTrue(self.port.GetPortString() == "tttH", "bit 0 is high")
    self.port.SetPin(0x1)
    self.assertTrue(self.port.GetPort() == 0, "read port register == 0")
    self.assertTrue(self.port.GetPin() == 0xe, "read pin register == 0xe")
    self.assertTrue(self.port.GetPortString() == "tttL", "bit 0 is low again")
    self.port.SetPin(0x2) # only port will change!
    self.assertTrue(self.port.GetPort() == 0x2, "read port register == 0x2")
    self.assertTrue(self.port.GetPin() == 0xe, "read pin register == 0xe")
    self.assertTrue(self.port.GetPortString() == "tthL", "bit 0 is low, bit 1 pullup")
    self.port.SetPin(0x2) # only port will change!
    self.assertTrue(self.port.GetPort() == 0, "read port register == 0")
    self.assertTrue(self.port.GetPin() == 0xe, "read pin register == 0xe")
    self.assertTrue(self.port.GetPortString() == "tttL", "bit 0 is low")

class TestCase_2(PyTestCase):
  
  """
  This testcase test a regular port without any outer connections, port has no pin toggle
  """

  def setUp(self):
    # create a avr core, type isn't important
    self.core = pysimulavr.AvrFactory.instance().makeDevice("atmega16")
    # create port with 4 bit and pin toggle feature
    self.port = pysimulavr.HWPort(self.core, "port", False, 4)

  def tearDown(self):
    del self.port
    del self.core

  def test_00(self):
    """check port initial state after reset"""
    self.assertTrue(self.port.GetPortString() == "tttt", "all output pins in tristate")
    self.assertTrue(self.port.GetPort() == 0, "read port register == 0")
    self.assertTrue(self.port.GetPin() == 0xf, "read pin register == 0xf")
    self.assertTrue(self.port.GetDdr() == 0, "read ddr register == 0")
    
  def test_01(self):
    """check, if pin toggle doesn't work"""
    self.assertTrue(self.port.GetPortString() == "tttt", "all output pins in tristate")
    self.port.SetDdr(0x1) # bit 0 is output
    self.assertTrue(self.port.GetPort() == 0, "read port register == 0")
    self.assertTrue(self.port.GetPin() == 0xe, "read pin register == 0xe")
    self.assertTrue(self.port.GetDdr() == 0x1, "read ddr register == 0x1")
    self.assertTrue(self.port.GetPortString() == "tttL", "bit 0 is low")
    self.port.SetPin(0x1)
    self.assertTrue(self.port.GetPort() == 0, "read port register == 0")
    self.assertTrue(self.port.GetPin() == 0xe, "read pin register == 0xe")
    self.assertTrue(self.port.GetPortString() == "tttL", "bit 0 is low")

class TestCase_3(PyTestCase):
  
  """
  This testcase test PinAtPort and alternate access to port pins
  """

  def setUp(self):
    # create a avr core, type isn't important
    self.core = pysimulavr.AvrFactory.instance().makeDevice("atmega16")
    # create port with 4 bit and pin toggle feature
    self.port = pysimulavr.HWPort(self.core, "port", False, 4)
    # create 2 special pins for port
    self.pinA = pysimulavr.PinAtPort(self.port, 0)
    self.pinB = pysimulavr.PinAtPort(self.port, 3)

  def tearDown(self):
    del self.pinB
    del self.pinA
    del self.port
    del self.core

  def test_00(self):
    """check pin initial state after reset"""
    self.assertTrue(self.port.GetPortString() == "tttt", "all output pins in tristate")
    self.assertTrue(self.port.GetPort() == 0, "read port register == 0")
    self.assertTrue(self.port.GetPin() == 0xf, "read pin register == 0xf")
    self.assertTrue(self.port.GetDdr() == 0, "read ddr register == 0")
    # get methods for pin A
    self.assertFalse(self.pinA.GetPort(), "port pin A is low")
    self.assertFalse(self.pinA.GetDdr(), "ddr pin A is input")
    # get methods for pin B
    self.assertFalse(self.pinB.GetPort(), "port pin B is low")
    self.assertFalse(self.pinB.GetDdr(), "ddr pin B is input")

  def test_01(self):
    """check override ddr functionality"""
    self.port.SetDdr(0xf) # all pins output
    self.assertTrue(self.port.GetPortString() == "LLLL", "all output pins low")
    self.assertTrue(self.port.GetPort() == 0, "read port register == 0")
    self.assertTrue(self.port.GetPin() == 0, "read pin register == 0")
    self.assertTrue(self.port.GetDdr() == 0xf, "read ddr register == 0xf")
    self.pinA.SetAlternateDdr(False) # preset override ddr to input
    self.assertTrue(self.port.GetPin() == 0, "read pin register == 0")
    self.assertTrue(self.port.GetPortString() == "LLLL", "all output pins low")
    self.pinA.SetUseAlternateDdr(True) # override ddr
    self.assertTrue(self.port.GetPort() == 0, "read port register == 0")
    self.assertTrue(self.port.GetPin() == 0x1, "read pin register == 0x1")
    self.assertTrue(self.port.GetDdr() == 0xf, "read ddr register == 0xf")
    self.assertTrue(self.port.GetPortString() == "LLLt", "pin 0 tristate")
    self.port.SetDdr(0xe) # no reaction expected
    self.assertTrue(self.port.GetPin() == 0x1, "read pin register == 0x1")
    self.assertTrue(self.port.GetDdr() == 0xe, "read ddr register == 0xe")
    self.assertTrue(self.port.GetPortString() == "LLLt", "pin 0 tristate")
    self.pinA.SetAlternateDdr(True) # preset override ddr to output
    self.assertTrue(self.port.GetPin() == 0, "read pin register == 0")
    self.assertTrue(self.port.GetDdr() == 0xe, "read ddr register == 0xe")
    self.assertTrue(self.port.GetPortString() == "LLLL", "all output pins low")
    self.pinA.SetUseAlternateDdr(False) # remove override ddr
    self.assertTrue(self.port.GetPin() == 0x1, "read pin register == 0x1")
    self.assertTrue(self.port.GetDdr() == 0xe, "read ddr register == 0xe")
    self.assertTrue(self.port.GetPortString() == "LLLt", "pin 0 tristate")

  def test_02(self):
    """check override ddr functionality with 2 pins"""
    self.port.SetDdr(0x3) # pin 0,1 as output
    self.assertTrue(self.port.GetPortString() == "ttLL", "2 pins tristate, 2 pins low")
    self.assertTrue(self.port.GetPort() == 0, "read port register == 0")
    self.assertTrue(self.port.GetPin() == 0xc, "read pin register == 0xc")
    self.assertTrue(self.port.GetDdr() == 0x3, "read ddr register == 0x3")
    self.pinA.SetAlternateDdr(False) # preset override ddr to input
    self.pinB.SetAlternateDdr(True) # preset override ddr to output
    self.assertTrue(self.port.GetPortString() == "ttLL", "2 pins tristate, 2 pins low")
    self.assertTrue(self.port.GetPin() == 0xc, "read pin register == 0xc")
    self.pinA.SetUseAlternateDdr(True) # override ddr
    self.assertTrue(self.port.GetPortString() == "ttLt", "3 pins tristate, 1 pin low")
    self.assertTrue(self.port.GetPin() == 0xd, "read pin register == 0xd")
    self.pinB.SetUseAlternateDdr(True) # override ddr
    self.assertTrue(self.port.GetPortString() == "LtLt", "2 pins tristate, 2 pins low")
    self.assertTrue(self.port.GetPin() == 0x5, "read pin register == 0x5")

  def test_03(self):
    """check override port functionality with 2 pins"""
    self.port.SetDdr(0x3) # pin 0,1 as output
    self.assertTrue(self.port.GetPortString() == "ttLL", "2 pins tristate, 2 pins low")
    self.assertTrue(self.port.GetPort() == 0, "read port register == 0")
    self.assertTrue(self.port.GetPin() == 0xc, "read pin register == 0xc")
    self.assertTrue(self.port.GetDdr() == 0x3, "read ddr register == 0x3")
    self.pinA.SetAlternatePort(True) # preset override port to high
    self.assertTrue(self.port.GetPortString() == "ttLL", "2 pins tristate, 2 pins low")
    self.assertTrue(self.port.GetPort() == 0, "read port register == 0")
    self.assertTrue(self.port.GetPin() == 0xc, "read pin register == 0xc")
    self.pinA.SetUseAlternatePort(True) # override port
    self.assertTrue(self.port.GetPortString() == "ttLH", "2 pins tristate, 1 pin low, 1 pin high")
    self.assertTrue(self.port.GetPort() == 0, "read port register == 0")
    self.assertTrue(self.port.GetPin() == 0xd, "read pin register == 0xd")
    self.pinB.SetAlternatePort(True) # preset override port to high
    self.pinB.SetUseAlternatePort(True) # override port
    self.assertTrue(self.port.GetPortString() == "ttLH", "2 pins tristate, 1 pin low, 1 pin high")
    self.assertTrue(self.port.GetPort() == 0, "read port register == 0")
    self.assertTrue(self.port.GetPin() == 0xd, "read pin register == 0xd")
    self.pinA.SetUseAlternatePort(False) # remove override port
    self.assertTrue(self.port.GetPortString() == "ttLL", "2 pins tristate, 2 pins low")
    self.assertTrue(self.port.GetPort() == 0, "read port register == 0")
    self.assertTrue(self.port.GetPin() == 0xc, "read pin register == 0xc")

  def test_04(self):
    """check override port if ddr set functionality with 2 pins"""
    self.port.SetDdr(0x3) # pin 0,1 as output
    self.assertTrue(self.port.GetPortString() == "ttLL", "2 pins tristate, 2 pins low")
    self.assertTrue(self.port.GetPort() == 0, "read port register == 0")
    self.assertTrue(self.port.GetPin() == 0xc, "read pin register == 0xc")
    self.assertTrue(self.port.GetDdr() == 0x3, "read ddr register == 0x3")
    self.pinA.SetAlternatePort(True) # preset override port to high
    self.pinA.SetUseAlternatePortIfDdrSet(True) # override port, if ddr is set
    self.assertTrue(self.port.GetPortString() == "ttLH", "2 pins tristate, 1 pin low, 1 pin high")
    self.assertTrue(self.port.GetPort() == 0, "read port register == 0")
    self.assertTrue(self.port.GetPin() == 0xd, "read pin register == 0xd")
    self.pinB.SetAlternatePort(True) # preset override port to high
    self.pinB.SetUseAlternatePortIfDdrSet(True) # override port, if ddr is set
    self.assertTrue(self.port.GetPortString() == "ttLH", "2 pins tristate, 1 pin low, 1 pin high")
    self.assertTrue(self.port.GetPort() == 0, "read port register == 0")
    self.assertTrue(self.port.GetPin() == 0xd, "read pin register == 0xd")
    self.port.SetDdr(0x2) # pin 1 as output
    self.assertTrue(self.port.GetPortString() == "ttLt", "3 pins tristate, 1 pin low")
    self.assertTrue(self.port.GetPin() == 0xd, "read pin register == 0xd")

class TestCase_4(PyTestCase):
  
  """
  This testcase test PinAtPort and alternate access to one port pin (multiple alternate use)
  """

  def setUp(self):
    # create a avr core, type isn't important
    self.core = pysimulavr.AvrFactory.instance().makeDevice("atmega16")
    # create port with 4 bit and pin toggle feature
    self.port = pysimulavr.HWPort(self.core, "port", False, 4)
    # create 2 special pins for port
    self.pinA = pysimulavr.PinAtPort(self.port, 0)
    self.pinB = pysimulavr.PinAtPort(self.port, 0)

  def tearDown(self):
    del self.pinB
    del self.pinA
    del self.port
    del self.core

  def test_00(self):
    """check pin initial state after reset"""
    self.assertTrue(self.port.GetPortString() == "tttt", "all output pins in tristate")
    self.assertTrue(self.port.GetPort() == 0, "read port register == 0")
    self.assertTrue(self.port.GetPin() == 0xf, "read pin register == 0xf")
    self.assertTrue(self.port.GetDdr() == 0, "read ddr register == 0")

  def test_01(self):
    """check override port if ddr set from first PinAtPort"""
    self.port.SetDdr(0x3) # pin 0,1 as output
    self.assertTrue(self.port.GetPortString() == "ttLL", "2 pins tristate, 2 pins low")
    self.assertTrue(self.port.GetPort() == 0, "read port register == 0")
    self.assertTrue(self.port.GetPin() == 0xc, "read pin register == 0xc")
    self.assertTrue(self.port.GetDdr() == 0x3, "read ddr register == 0x3")
    self.pinA.SetAlternatePort(True) # preset override port to high for first PinAtPort
    self.pinA.SetUseAlternatePortIfDdrSet(True) # override first PinAtPort, if ddr is set
    self.assertTrue(self.port.GetPortString() == "ttLH", "2 pins tristate, 1 pin low, 1 pin high")
    self.assertTrue(self.port.GetPort() == 0, "read port register == 0")
    self.assertTrue(self.port.GetPin() == 0xd, "read pin register == 0xd")
    self.pinA.SetUseAlternatePortIfDdrSet(False) # remove override port
    self.assertTrue(self.port.GetPortString() == "ttLL", "2 pins tristate, 2 pins low")
    self.assertTrue(self.port.GetPort() == 0, "read port register == 0")
    self.assertTrue(self.port.GetPin() == 0xc, "read pin register == 0xc")
    self.assertTrue(self.port.GetDdr() == 0x3, "read ddr register == 0x3")
    self.pinB.SetAlternatePort(False) # preset override port to low for second PinAtPort
    self.pinB.SetUseAlternatePortIfDdrSet(True) # override second PinAtPort, if ddr is set
    print ">>>", self.port.GetPortString(), "<<<"
    self.assertTrue(self.port.GetPortString() == "ttLL", "2 pins tristate, 2 pins low")
    self.assertTrue(self.port.GetPort() == 0, "read port register == 0")
    self.assertTrue(self.port.GetPin() == 0xc, "read pin register == 0xc")
    self.assertTrue(self.port.GetDdr() == 0x3, "read ddr register == 0x3")

if __name__ == '__main__':
  
  from unittest import TextTestRunner
  tests = PyTestLoader("portio").loadTestsFromTestCase(TestCase_1)
  TextTestRunner(verbosity = 2).run(tests)

# EOF