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Introduction
SimulPIC is a command line simulator for the PIC16F84 microchip. It provides all standard functions for debugging, with the possibility to provide the transitions of the input pins from command line or from input file. It is possible to write to file both the transitions of the output pins and the states of the pin samples with variable period of sampling.
1. Simulation
1.1. Transitions of the incomes
The simulation is tied to the instruction cycle (4 tosc), whose duration depends on the clock frequency, which can be defined with a command. The temporal resolution of the simulation puts limits on the possible input transitions. With reference to the figure below, it is assumed that the transition to the running step (B) happens between Q2 of the cycle of the previous instruction (A) and the end of Q1 of the current, so that the new value is immediately available for reading (instruction B).
| Instruction Cycle |
|<--------------------->|
| |
| Q1 | Q2 | Q3 | Q4 | Q1 | Q2 | Q3 | Q4 |
|__ __ __ __ |__ __ __ __ |
CLKIN / \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__|
| | |
| _________________|_______________________|
PIN |_____/_/_/_/_/_/_/_/_/_/_/_/ |
| |
| <-----Transition------> |
| |
|<----- instr. A ------>|<----- instr. B ------>|
(Currently running)
1.2. RTCC in 'Counter Mode'
Multiple transitions cannot be simulated--within the same cycle of instruction--of pin RA4/RTCC (with a prescaler of 1:256 the detailed list allows hundreds of transitions). The supplied transition is assumed to happen between Q1 and Q4 of the running cycle. After all, in counter mode without prescaler, RTCC is increased at most every two cycles of instruction.
1.3. Configuration Fuses
The fuses for Power-up timer, code protection, and oscillator selection are not simulated for obvious reasons. The only one considered is the Watchdog Timer fuse.
1.4. Not controlled input ports
To make it simple, the pins configured as non-controlled input (HZ) are not read as logical ones, which means, when previewed, the pull-ups are considered always active.
1.5. EEPROM
The cycle of writing to the program memory is not simulated, while the EEPROM memory is simulated with a writing cycle of 10ms (nominal time).
1.6. Watchdog
The watchdog period is assumed as 18ms (nominal time).
2. File formats
2.1. Input files
The input file contains all transitions of the pins with the following syntax:
{ [# <Comment>] }
"begin"
{ [# <Comment>]
<Time> [MCLR = m] [RA = ppppp] [RAn = p] [RB= pppppppp] [RBn = p] }
"end"
with: n = {0..4} for port A
{0..7} for port B
m = 0 : forces logical level 0 (RESET)
1 : forces logical level 1
p = 0 : forces logical level 0
1 : forces logical level 1
- : does not force any logical level
u : conserves the unchanged previous state
If one tries to force the level of an output pin
during the simulation, an error message will shop up.
The succession of time has to be strictly monotonous; the transitions supplied in the same cycle of instruction must be found in single line. The file is compiled with the IEC compiler IEC to a format that is readable for the simulator. IEC marks all syntactic errors.
2.2. Output File: Report File
The individual transitions of the output ports is expected to be in a file (Report File) with the following format:
>aaaaa bbbbbbbb TIME - register transitions of the ports
a,b = 0 : output pin on logical level 0
1 : output pin on logical level 1
. : input pin
TIME : time in ms.
<aaaaa bbbbbbbb TIME - changes of the input pin states
a,b = 0 : input pin on logical level 0
1 : input pin on logical level 1
- : input pin, not controlled
. : output pin
Taaaaa bbbbbbbb TIME - change of the tristate states
a,b = 0 : Relative output pin.
1 : Relative input pin.
2.3. Output file, Graphic File
On command line, one can monitor the states of the output pins with periods of fixed sampling.
In the following an example pin RA1 is at logical level 1, pin RA0 on logical level 0, while RB6 has a transition from high level to low. The signals of the input pins are:
----------------------------------------------------------------------------
RA4 RA3 RA2 RA1 RA0 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 Time
. . . | | . | . . . . . . 0.1096
. . . | | . | . . . . . . 0.1140
. . . | | . | . . . . . . 0.1184
. . . | | . | . . . . . . 0.1228
. . . | | . | . . . . . . 0.1272
. . . | | . | . . . . . . 0.1316
. . . | | . | . . . . . . 0.1360
. . . | | . | . . . . . . 0.1404
. . . | | . | . . . . . . 0.1448
----------------------------------------------------------------------------
3. Simulator commands
At the command prompt, the running time is shown which increases for every cycle of simulated instruction. Loading a new program resets the clock.
"h" shows help
"l" loads object file with IHX8M format into program memory, with fuse WDTE
"dr" shows the states of the special registers, of the processor (SLEEP, RESET, NORMAL, and the next instruction to be executed
"dg" shows the contents of the general registers
"dee" shows the contents of the EEPROM Data Memory
"dpm" shows the contents of the Program Memory
"ds" shows the contents of the stack (the simulation even shows error messages like "Stack overflow" and "Pop on empty stack")
"dp" shows the actual states of the input pins.
"d [<addr>]" disassemble ten instructions from PC on, or addr
"s [<num>]" simulates one (or <num>) instruction cycles of the PIC16C84
"g <time>" proceeds with the simulation until <time> in ms
"bp [<address>]" set/clear breakpoint.
"pa ppppp" configures the states of the port A pins:
"pm p" forces a logical level onto pin MCLR (p = 0,1)
"io [<filename>]" opens the input file containing the pin transitions
"ic" closes the input file containing the pin transitions
"ro [<filename>]" opens the output file showing only the transitions
"rc" closes the output file showing only the transitions
"eo [<filename>]" opens the "Graphic File"
"ec" closes "Graphic File"
"por" generates a Power-On-Reset and resets the simulation clock
"q" quits the simulator
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