1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
|
// -*- Mode: Go; indent-tabs-mode: t -*-
/*
* Copyright (C) 2020 Canonical Ltd
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 3 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
*/
package builtin
const fpgaSummary = `allows access to the FPGA subsystem`
const fpgaBaseDeclarationSlots = `
fpga:
allow-installation:
slot-snap-type:
- core
deny-auto-connection: true
`
const fpgaConnectedPlugAppArmor = `
# Description: Can access fpga subsystem.
# Devices
/dev/fpga[0-9]* rw,
# /sys/class/fpga_* specified by:
# https://github.com/torvalds/linux/blob/master/Documentation/ABI/testing/sysfs-class-fpga-manager
# https://github.com/torvalds/linux/blob/master/Documentation/ABI/testing/sysfs-class-fpga-region
# https://github.com/torvalds/linux/blob/master/Documentation/ABI/testing/sysfs-class-fpga-bridge
/sys/class/fpga_manager/fpga[0-9]*/{name,state,status} r,
/sys/class/fpga_region/region[0-9]*/compat_id r,
/sys/class/fpga_bridge/bridge[0-9]*/{name,state} r,
# Xilinx zynqmp FPGA, created by zynqmp_fpga_manager driver
# https://github.com/torvalds/linux/blob/master/drivers/fpga/zynqmp-fpga.c
/sys/devices/platform/firmware:zynqmp-firmware/firmware:zynqmp-firmware:pcap/fpga_manager/fpga[0-9]*/{name,state,status} r,
/sys/devices/platform/firmware:zynqmp-firmware/firmware:zynqmp-firmware:pcap/fpga_manager/fpga[0-9]*/firmware w,
/sys/devices/platform/firmware:zynqmp-firmware/firmware:zynqmp-firmware:pcap/fpga_manager/fpga[0-9]*/{flags,key} rw,
/sys/devices/platform/fpga-full/fpga_region/region[0-9]*/compat_id r,
# Xilinx zynqmp module parameters (not upstreamed yet)
# https://github.com/Xilinx/linux-xlnx/blob/master/drivers/fpga/zynqmp-fpga.c#L36
/sys/module/zynqmp_fpga/parameters/readback_type rw,
`
var fpgaConnectedPlugUDev = []string{
`SUBSYSTEM=="misc", KERNEL=="fpga[0-9]*"`,
}
func init() {
registerIface(&commonInterface{
name: "fpga",
summary: fpgaSummary,
implicitOnCore: true,
implicitOnClassic: true,
baseDeclarationSlots: fpgaBaseDeclarationSlots,
connectedPlugAppArmor: fpgaConnectedPlugAppArmor,
connectedPlugUDev: fpgaConnectedPlugUDev,
})
}
|