package info
(click to toggle)
swiftlang 6.0.3-2
- links: PTS, VCS
- area: main
- in suites: forky, sid, trixie
- size: 2,519,992 kB
- sloc: cpp: 9,107,863; ansic: 2,040,022; asm: 1,135,751; python: 296,500; objc: 82,456; f90: 60,502; lisp: 34,951; pascal: 19,946; sh: 18,133; perl: 7,482; ml: 4,937; javascript: 4,117; makefile: 3,840; awk: 3,535; xml: 914; fortran: 619; cs: 573; ruby: 573
Folder: kernel-name-restriction
 |
.. (parent) | |||
|
d | rwxr-xr-x | 28 | otherdir |
|
d | rwxr-xr-x | 83 | some |
|
d | rwxr-xr-x | 31 | somedir |
|
d | rwxr-xr-x | 69 | uppercase |
 |
- | rw-r--r-- | 26 | Verilog.cl |
|
- | rw-r--r-- | 25 | kernel.cl |
|
- | rw-r--r-- | 26 | kernel.h |
|
- | rw-r--r-- | 31 | other_Verilog.cl |
|
- | rw-r--r-- | 29 | otherthing.cl |
|
- | rw-r--r-- | 29 | some_kernel.cl |
|
- | rw-r--r-- | 24 | thing.h |
|
- | rw-r--r-- | 27 | verilog.h |
|
- | rw-r--r-- | 24 | vhdl.CL |
|
- | rw-r--r-- | 24 | vhdl.h |
|
- | rw-r--r-- | 32 | vhdl_number_two.cl |