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|
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple aarch64 -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s
---
name: shl_by_ge_bw
alignment: 4
tracksRegLiveness: true
liveins:
- { reg: '$w0' }
body: |
bb.1:
liveins: $w0
; CHECK-LABEL: name: shl_by_ge_bw
; CHECK: liveins: $w0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[DEF]](s16)
; CHECK-NEXT: $w0 = COPY [[ANYEXT]](s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%1:_(s32) = COPY $w0
%0:_(s16) = G_TRUNC %1(s32)
%2:_(s16) = G_CONSTANT i16 20
%3:_(s16) = G_SHL %0, %2(s16)
%4:_(s32) = G_ANYEXT %3(s16)
$w0 = COPY %4(s32)
RET_ReallyLR implicit $w0
...
---
name: lshr_by_ge_bw
alignment: 4
tracksRegLiveness: true
liveins:
- { reg: '$w0' }
body: |
bb.1:
liveins: $w0
; CHECK-LABEL: name: lshr_by_ge_bw
; CHECK: liveins: $w0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[DEF]](s16)
; CHECK-NEXT: $w0 = COPY [[ANYEXT]](s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%1:_(s32) = COPY $w0
%0:_(s16) = G_TRUNC %1(s32)
%2:_(s16) = G_CONSTANT i16 16
%3:_(s16) = G_LSHR %0, %2(s16)
%4:_(s32) = G_ANYEXT %3(s16)
$w0 = COPY %4(s32)
RET_ReallyLR implicit $w0
...
---
name: ashr_by_ge_bw
alignment: 4
tracksRegLiveness: true
liveins:
- { reg: '$w0' }
body: |
bb.1:
liveins: $w0
; CHECK-LABEL: name: ashr_by_ge_bw
; CHECK: liveins: $w0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[DEF]](s16)
; CHECK-NEXT: $w0 = COPY [[ANYEXT]](s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%1:_(s32) = COPY $w0
%0:_(s16) = G_TRUNC %1(s32)
%2:_(s16) = G_CONSTANT i16 20
%3:_(s16) = G_ASHR %0, %2(s16)
%4:_(s32) = G_ANYEXT %3(s16)
$w0 = COPY %4(s32)
RET_ReallyLR implicit $w0
...
---
name: shl_by_ge_bw_vector
alignment: 4
tracksRegLiveness: true
liveins:
- { reg: '$q0' }
body: |
bb.1:
liveins: $q0
; CHECK-LABEL: name: shl_by_ge_bw_vector
; CHECK: liveins: $q0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %shl:_(<4 x s32>) = G_IMPLICIT_DEF
; CHECK-NEXT: $q0 = COPY %shl(<4 x s32>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
%1:_(<4 x s32>) = COPY $q0
%0:_(s32) = G_CONSTANT i32 32
%bv:_(<4 x s32>) = G_BUILD_VECTOR %0, %0, %0, %0
%shl:_(<4 x s32>) = G_SHL %1, %bv(<4 x s32>)
$q0 = COPY %shl(<4 x s32>)
RET_ReallyLR implicit $q0
...
---
name: shl_by_ge_bw_vector_partial
alignment: 4
tracksRegLiveness: true
liveins:
- { reg: '$q0' }
body: |
bb.1:
liveins: $q0
; CHECK-LABEL: name: shl_by_ge_bw_vector_partial
; CHECK: liveins: $q0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
; CHECK-NEXT: %small:_(s32) = G_CONSTANT i32 4
; CHECK-NEXT: %bv:_(<4 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32), [[C]](s32), %small(s32)
; CHECK-NEXT: %shl:_(<4 x s32>) = G_SHL [[COPY]], %bv(<4 x s32>)
; CHECK-NEXT: $q0 = COPY %shl(<4 x s32>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
%1:_(<4 x s32>) = COPY $q0
%0:_(s32) = G_CONSTANT i32 32
%small:_(s32) = G_CONSTANT i32 4
%bv:_(<4 x s32>) = G_BUILD_VECTOR %0, %0, %0, %small
%shl:_(<4 x s32>) = G_SHL %1, %bv(<4 x s32>)
$q0 = COPY %shl(<4 x s32>)
RET_ReallyLR implicit $q0
...
|
