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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -debugify-and-strip-all-safe -O0 -mtriple=aarch64-unknown-unknown -verify-machineinstrs -run-pass=legalizer %s -o - | FileCheck %s
--- |
target datalayout = "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
define void @snork() {
bb:
br label %bb1
bb1: ; preds = %bb3, %bb
%lsr.iv = phi i16* [ %scevgep, %bb3 ], [ undef, %bb ]
%tmp = phi i1 [ %tmp9, %bb3 ], [ undef, %bb ]
br i1 %tmp, label %bb10, label %bb3
bb3: ; preds = %bb1
%tmp5 = getelementptr i16, i16* null, i64 2
%tmp6 = load i16, i16* %lsr.iv, align 2, !tbaa !0
%tmp7 = icmp eq i16 %tmp6, -1
%tmp8 = load i16, i16* %tmp5, align 2, !tbaa !0
%tmp9 = icmp eq i16 %tmp8, -1
%scevgep = getelementptr i16, i16* %lsr.iv, i64 2
br i1 %tmp7, label %bb10, label %bb1
bb10: ; preds = %bb3, %bb1
ret void
}
!0 = !{!1, !1, i64 0}
!1 = !{!"short", !2, i64 0}
!2 = !{!"omnipotent char", !3, i64 0}
!3 = !{!"Simple C/C++ TBAA"}
...
---
name: snork
alignment: 16
tracksRegLiveness: true
frameInfo:
maxAlignment: 1
body: |
; CHECK-LABEL: name: snork
; CHECK: bb.0.bb:
; CHECK-NEXT: successors: %bb.1(0x80000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK-NEXT: [[INTTOPTR:%[0-9]+]]:_(p0) = G_INTTOPTR [[C]](s64)
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(p0) = G_IMPLICIT_DEF
; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1.bb1:
; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[PHI:%[0-9]+]]:_(p0) = G_PHI %6(p0), %bb.2, [[DEF]](p0), %bb.0
; CHECK-NEXT: [[PHI1:%[0-9]+]]:_(s16) = G_PHI %22(s16), %bb.2, [[DEF1]](s16), %bb.0
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[PHI1]](s16)
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C1]]
; CHECK-NEXT: G_BRCOND [[AND]](s32), %bb.3
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.bb3:
; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.1(0x40000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[INTTOPTR]], [[C2]](s64)
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s16) = G_LOAD [[PHI]](p0) :: (load (s16) from %ir.lsr.iv)
; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[LOAD]](s16)
; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[ZEXT]](s32), [[C3]]
; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(s16) = G_LOAD [[PTR_ADD]](p0) :: (load (s16) from %ir.tmp5)
; CHECK-NEXT: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[LOAD1]](s16)
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[ZEXT1]](s32), [[COPY]]
; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[PHI]], [[C2]](s64)
; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C4]]
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[ICMP1]](s32)
; CHECK-NEXT: G_BRCOND [[AND1]](s32), %bb.3
; CHECK-NEXT: G_BR %bb.1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.3.bb10:
; CHECK-NEXT: RET_ReallyLR
bb.1.bb:
%3:_(s64) = G_CONSTANT i64 0
%2:_(p0) = G_INTTOPTR %3(s64)
%7:_(s16) = G_CONSTANT i16 -1
%12:_(p0) = G_IMPLICIT_DEF
%13:_(s1) = G_IMPLICIT_DEF
bb.2.bb1:
%0:_(p0) = G_PHI %11(p0), %bb.3, %12(p0), %bb.1
%1:_(s1) = G_PHI %10(s1), %bb.3, %13(s1), %bb.1
G_BRCOND %1(s1), %bb.4
bb.3.bb3:
%4:_(s64) = G_CONSTANT i64 4
%5:_(p0) = G_PTR_ADD %2, %4(s64)
%6:_(s16) = G_LOAD %0(p0) :: (load (s16) from %ir.lsr.iv)
%8:_(s1) = G_ICMP intpred(eq), %6(s16), %7
%9:_(s16) = G_LOAD %5(p0) :: (load (s16) from %ir.tmp5)
%10:_(s1) = G_ICMP intpred(eq), %9(s16), %7
%11:_(p0) = G_PTR_ADD %0, %4(s64)
G_BRCOND %8(s1), %bb.4
G_BR %bb.2
bb.4.bb10:
RET_ReallyLR
...
|
