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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple aarch64 -run-pass=aarch64-postlegalizer-combiner --aarch64postlegalizercombiner-only-enable-rule="rotate_out_of_range" -verify-machineinstrs %s -o - | FileCheck %s
# REQUIRES: asserts
# Check that we simplify the constant rotate amount to be in range.
---
name: rotl
alignment: 4
legalized: true
tracksRegLiveness: true
liveins:
- { reg: '$w0' }
body: |
bb.1.entry:
liveins: $w0
; CHECK-LABEL: name: rotl
; CHECK: liveins: $w0
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; CHECK: [[ROTL:%[0-9]+]]:_(s32) = G_ROTL [[COPY]], [[C]](s64)
; CHECK: $w0 = COPY [[ROTL]](s32)
; CHECK: RET_ReallyLR implicit $w0
%0:_(s32) = COPY $w0
%5:_(s64) = G_CONSTANT i64 -16
%2:_(s32) = G_ROTL %0, %5(s64)
$w0 = COPY %2(s32)
RET_ReallyLR implicit $w0
...
---
name: rotr
alignment: 4
legalized: true
tracksRegLiveness: true
liveins:
- { reg: '$w0' }
body: |
bb.1.entry:
liveins: $w0
; CHECK-LABEL: name: rotr
; CHECK: liveins: $w0
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; CHECK: [[ROTR:%[0-9]+]]:_(s32) = G_ROTR [[COPY]], [[C]](s64)
; CHECK: $w0 = COPY [[ROTR]](s32)
; CHECK: RET_ReallyLR implicit $w0
%0:_(s32) = COPY $w0
%5:_(s64) = G_CONSTANT i64 -16
%2:_(s32) = G_ROTR %0, %5(s64)
$w0 = COPY %2(s32)
RET_ReallyLR implicit $w0
...
---
name: rotl_bitwidth_cst
alignment: 4
legalized: true
tracksRegLiveness: true
liveins:
- { reg: '$w0' }
body: |
bb.1.entry:
liveins: $w0
; CHECK-LABEL: name: rotl_bitwidth_cst
; CHECK: liveins: $w0
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK: [[ROTL:%[0-9]+]]:_(s32) = G_ROTL [[COPY]], [[C]](s64)
; CHECK: $w0 = COPY [[ROTL]](s32)
; CHECK: RET_ReallyLR implicit $w0
%0:_(s32) = COPY $w0
%5:_(s64) = G_CONSTANT i64 32
%2:_(s32) = G_ROTL %0, %5(s64)
$w0 = COPY %2(s32)
RET_ReallyLR implicit $w0
...
---
name: rotl_bitwidth_minus_one_cst
alignment: 4
legalized: true
tracksRegLiveness: true
liveins:
- { reg: '$w0' }
body: |
bb.1.entry:
liveins: $w0
; CHECK-LABEL: name: rotl_bitwidth_minus_one_cst
; CHECK: liveins: $w0
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 31
; CHECK: [[ROTL:%[0-9]+]]:_(s32) = G_ROTL [[COPY]], [[C]](s64)
; CHECK: $w0 = COPY [[ROTL]](s32)
; CHECK: RET_ReallyLR implicit $w0
%0:_(s32) = COPY $w0
%5:_(s64) = G_CONSTANT i64 31
%2:_(s32) = G_ROTL %0, %5(s64)
$w0 = COPY %2(s32)
RET_ReallyLR implicit $w0
...
|
