File: prelegalizer-combiner-addo-zero.mir

package info (click to toggle)
swiftlang 6.0.3-2
  • links: PTS, VCS
  • area: main
  • in suites: forky, sid, trixie
  • size: 2,519,992 kB
  • sloc: cpp: 9,107,863; ansic: 2,040,022; asm: 1,135,751; python: 296,500; objc: 82,456; f90: 60,502; lisp: 34,951; pascal: 19,946; sh: 18,133; perl: 7,482; ml: 4,937; javascript: 4,117; makefile: 3,840; awk: 3,535; xml: 914; fortran: 619; cs: 573; ruby: 573
file content (136 lines) | stat: -rw-r--r-- 4,877 bytes parent folder | download | duplicates (3)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple aarch64 -debugify-and-strip-all-safe -run-pass=aarch64-prelegalizer-combiner --aarch64prelegalizercombiner-only-enable-rule="addo_by_0" -global-isel -verify-machineinstrs %s -o - | FileCheck %s
# REQUIRES: asserts

# (G_*ADDO x, 0) -> x + no carry

...
---
name:            uadd_zero
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $w0, $w1
    ; CHECK-LABEL: name: uadd_zero
    ; CHECK: liveins: $w0, $w1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: %lhs:_(s32) = COPY $w0
    ; CHECK-NEXT: %add:_(s32) = COPY %lhs(s32)
    ; CHECK-NEXT: %o:_(s1) = G_CONSTANT i1 false
    ; CHECK-NEXT: %o_wide:_(s32) = G_ZEXT %o(s1)
    ; CHECK-NEXT: $w0 = COPY %add(s32)
    ; CHECK-NEXT: $w1 = COPY %o_wide(s32)
    ; CHECK-NEXT: RET_ReallyLR implicit $w0
    %lhs:_(s32) = COPY $w0
    %zero:_(s32) = G_CONSTANT i32 0
    %add:_(s32), %o:_(s1) = G_UADDO %lhs, %zero
    %o_wide:_(s32) = G_ZEXT %o(s1)
    $w0 = COPY %add(s32)
    $w1 = COPY %o_wide
    RET_ReallyLR implicit $w0
...
---
name:            sadd_zero
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $w0, $w1
    ; CHECK-LABEL: name: sadd_zero
    ; CHECK: liveins: $w0, $w1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: %lhs:_(s32) = COPY $w0
    ; CHECK-NEXT: %add:_(s32) = COPY %lhs(s32)
    ; CHECK-NEXT: %o:_(s1) = G_CONSTANT i1 false
    ; CHECK-NEXT: %o_wide:_(s32) = G_ZEXT %o(s1)
    ; CHECK-NEXT: $w0 = COPY %add(s32)
    ; CHECK-NEXT: $w1 = COPY %o_wide(s32)
    ; CHECK-NEXT: RET_ReallyLR implicit $w0
    %lhs:_(s32) = COPY $w0
    %zero:_(s32) = G_CONSTANT i32 0
    %add:_(s32), %o:_(s1) = G_SADDO %lhs, %zero
    %o_wide:_(s32) = G_ZEXT %o(s1)
    $w0 = COPY %add(s32)
    $w1 = COPY %o_wide
    RET_ReallyLR implicit $w0
...
---
name:            wrong_cst
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $w0, $w1
    ; CHECK-LABEL: name: wrong_cst
    ; CHECK: liveins: $w0, $w1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: %lhs:_(s32) = COPY $w0
    ; CHECK-NEXT: %not_zero:_(s32) = G_CONSTANT i32 3
    ; CHECK-NEXT: %add:_(s32), %o:_(s1) = G_UADDO %lhs, %not_zero
    ; CHECK-NEXT: %o_wide:_(s32) = G_ZEXT %o(s1)
    ; CHECK-NEXT: $w0 = COPY %add(s32)
    ; CHECK-NEXT: $w1 = COPY %o_wide(s32)
    ; CHECK-NEXT: RET_ReallyLR implicit $w0
    %lhs:_(s32) = COPY $w0
    %not_zero:_(s32) = G_CONSTANT i32 3
    %add:_(s32), %o:_(s1) = G_UADDO %lhs, %not_zero
    %o_wide:_(s32) = G_ZEXT %o(s1)
    $w0 = COPY %add(s32)
    $w1 = COPY %o_wide
    RET_ReallyLR implicit $w0
...
---
name:            uadd_vec_zero
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $q0, $x0
    ; CHECK-LABEL: name: uadd_vec_zero
    ; CHECK: liveins: $q0, $x0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: %lhs:_(<2 x s64>) = COPY $q0
    ; CHECK-NEXT: %zero:_(s64) = G_CONSTANT i64 0
    ; CHECK-NEXT: %add:_(<2 x s64>) = COPY %lhs(<2 x s64>)
    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 false
    ; CHECK-NEXT: %o:_(<2 x s1>) = G_BUILD_VECTOR [[C]](s1), [[C]](s1)
    ; CHECK-NEXT: %o_elt_0:_(s1) = G_EXTRACT_VECTOR_ELT %o(<2 x s1>), %zero(s64)
    ; CHECK-NEXT: %o_wide:_(s64) = G_ZEXT %o_elt_0(s1)
    ; CHECK-NEXT: $q0 = COPY %add(<2 x s64>)
    ; CHECK-NEXT: $x0 = COPY %o_wide(s64)
    ; CHECK-NEXT: RET_ReallyLR implicit $q0
    %lhs:_(<2 x s64>) = COPY $q0
    %zero:_(s64) = G_CONSTANT i64 0
    %zero_vec:_(<2 x s64>) = G_BUILD_VECTOR %zero, %zero
    %add:_(<2 x s64>), %o:_(<2 x s1>) = G_UADDO %lhs, %zero_vec
    %o_elt_0:_(s1) = G_EXTRACT_VECTOR_ELT %o:_(<2 x s1>), %zero:_(s64)
    %o_wide:_(s64) = G_ZEXT %o_elt_0
    $q0 = COPY %add(<2 x s64>)
    $x0 = COPY %o_wide
    RET_ReallyLR implicit $q0
...
---
name:            sadd_vec_zero
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $q0, $x0
    ; CHECK-LABEL: name: sadd_vec_zero
    ; CHECK: liveins: $q0, $x0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: %lhs:_(<2 x s64>) = COPY $q0
    ; CHECK-NEXT: %zero:_(s64) = G_CONSTANT i64 0
    ; CHECK-NEXT: %add:_(<2 x s64>) = COPY %lhs(<2 x s64>)
    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 false
    ; CHECK-NEXT: %o:_(<2 x s1>) = G_BUILD_VECTOR [[C]](s1), [[C]](s1)
    ; CHECK-NEXT: %o_elt_0:_(s1) = G_EXTRACT_VECTOR_ELT %o(<2 x s1>), %zero(s64)
    ; CHECK-NEXT: %o_wide:_(s64) = G_ZEXT %o_elt_0(s1)
    ; CHECK-NEXT: $q0 = COPY %add(<2 x s64>)
    ; CHECK-NEXT: $x0 = COPY %o_wide(s64)
    ; CHECK-NEXT: RET_ReallyLR implicit $q0
    %lhs:_(<2 x s64>) = COPY $q0
    %zero:_(s64) = G_CONSTANT i64 0
    %zero_vec:_(<2 x s64>) = G_BUILD_VECTOR %zero, %zero
    %add:_(<2 x s64>), %o:_(<2 x s1>) = G_SADDO %lhs, %zero_vec
    %o_elt_0:_(s1) = G_EXTRACT_VECTOR_ELT %o:_(<2 x s1>), %zero:_(s64)
    %o_wide:_(s64) = G_ZEXT %o_elt_0
    $q0 = COPY %add(<2 x s64>)
    $x0 = COPY %o_wide
    RET_ReallyLR implicit $q0