1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
|
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple aarch64-apple-ios -run-pass=aarch64-prelegalizer-combiner %s -o - -verify-machineinstrs | FileCheck %s
# Check that we insert the divrem at the place of the G_UDIV, not the G_UREM.
---
name: divrem_use_before_def
alignment: 4
tracksRegLiveness: true
liveins:
- { reg: '$x0' }
body: |
; CHECK-LABEL: name: divrem_use_before_def
; CHECK: bb.0:
; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)
; CHECK-NEXT: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s1) = G_IMPLICIT_DEF
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
; CHECK-NEXT: G_BRCOND [[DEF]](s1), %bb.2
; CHECK-NEXT: G_BR %bb.1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1:
; CHECK-NEXT: successors: %bb.2(0x80000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[C2]](s32)
; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
; CHECK-NEXT: [[FREEZE:%[0-9]+]]:_(s64) = G_FREEZE [[C3]]
; CHECK-NEXT: [[UDIV:%[0-9]+]]:_(s64) = G_UDIV [[FREEZE]], [[C]]
; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[ZEXT]], [[C1]](s64)
; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[SHL]], [[UDIV]]
; CHECK-NEXT: G_STORE [[ADD]](s64), [[COPY]](p0) :: (store (s64))
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2:
bb.1:
liveins: $x0
%0:_(p0) = COPY $x0
%1:_(s1) = G_IMPLICIT_DEF
%2:_(s64) = G_IMPLICIT_DEF
%4:_(s64) = G_CONSTANT i64 0
%12:_(s64) = G_CONSTANT i64 32
G_BRCOND %1(s1), %bb.3
G_BR %bb.2
bb.2:
%3:_(s32) = G_TRUNC %2(s64)
%5:_(s32) = G_TRUNC %4(s64)
%6:_(s32) = G_UDIV %3, %5
%7:_(s64) = G_ZEXT %6(s32)
%8:_(s32) = COPY %3(s32)
%9:_(s32) = COPY %5(s32)
%10:_(s32) = G_UREM %8, %9
%11:_(s64) = G_ZEXT %10(s32)
%13:_(s64) = nuw G_SHL %11, %12(s64)
%14:_(s64) = G_OR %2, %13
%15:_(s64) = G_FREEZE %14
%16:_(s64) = G_UDIV %15, %4
%17:_(s64) = G_SHL %7, %12(s64)
%18:_(s64) = G_ADD %17, %16
G_STORE %18(s64), %0(p0) :: (store (s64))
bb.3:
...
|
