1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
|
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=aarch64 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
---
name: v2s32_fmul_indexed
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
liveins:
- { reg: '$d0' }
- { reg: '$x0' }
frameInfo:
maxAlignment: 1
body: |
bb.1:
liveins: $d0, $x0
; CHECK-LABEL: name: v2s32_fmul_indexed
; CHECK: liveins: $d0, $x0
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK: [[COPY1:%[0-9]+]]:gpr64sp = COPY $x0
; CHECK: [[LDRDui:%[0-9]+]]:fpr64 = LDRDui [[COPY1]], 0 :: (load (<2 x s32>), align 4)
; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[LDRDui]], %subreg.dsub
; CHECK: [[FMULv2i32_indexed:%[0-9]+]]:fpr64 = nofpexcept FMULv2i32_indexed [[COPY]], [[INSERT_SUBREG]], 0
; CHECK: $d0 = COPY [[FMULv2i32_indexed]]
; CHECK: RET_ReallyLR implicit $d0
%0:fpr(<2 x s32>) = COPY $d0
%1:gpr(p0) = COPY $x0
%2:fpr(<2 x s32>) = G_LOAD %1(p0) :: (load (<2 x s32>), align 4)
%9:fpr(<2 x s32>) = G_IMPLICIT_DEF
%10:fpr(<4 x s32>) = G_CONCAT_VECTORS %2(<2 x s32>), %9(<2 x s32>)
%8:gpr(s64) = G_CONSTANT i64 0
%5:fpr(<2 x s32>) = G_DUPLANE32 %10, %8(s64)
%7:fpr(<2 x s32>) = G_FMUL %0, %5
$d0 = COPY %7(<2 x s32>)
RET_ReallyLR implicit $d0
...
|
