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|
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=aarch64 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
...
---
name: fcmeq
alignment: 4
legalized: true
regBankSelected: true
body: |
bb.0:
; CHECK-LABEL: name: fcmeq
; CHECK: %lhs:fpr128 = COPY $q0
; CHECK: %rhs:fpr128 = COPY $q1
; CHECK: %fcmp:fpr128 = nofpexcept FCMEQv2f64 %lhs, %rhs
; CHECK: $q0 = COPY %fcmp
; CHECK: RET_ReallyLR implicit $q0
%lhs:fpr(<2 x s64>) = COPY $q0
%rhs:fpr(<2 x s64>) = COPY $q1
%fcmp:fpr(<2 x s64>) = G_FCMEQ %lhs, %rhs(<2 x s64>)
$q0 = COPY %fcmp(<2 x s64>)
RET_ReallyLR implicit $q0
...
---
name: fcmge
alignment: 4
legalized: true
regBankSelected: true
body: |
bb.0:
; CHECK-LABEL: name: fcmge
; CHECK: %lhs:fpr128 = COPY $q0
; CHECK: %rhs:fpr128 = COPY $q1
; CHECK: %fcmp:fpr128 = nofpexcept FCMGEv2f64 %lhs, %rhs
; CHECK: $q0 = COPY %fcmp
; CHECK: RET_ReallyLR implicit $q0
%lhs:fpr(<2 x s64>) = COPY $q0
%rhs:fpr(<2 x s64>) = COPY $q1
%fcmp:fpr(<2 x s64>) = G_FCMGE %lhs, %rhs(<2 x s64>)
$q0 = COPY %fcmp(<2 x s64>)
RET_ReallyLR implicit $q0
...
---
name: fcmgt
alignment: 4
legalized: true
regBankSelected: true
body: |
bb.0:
; CHECK-LABEL: name: fcmgt
; CHECK: %lhs:fpr128 = COPY $q0
; CHECK: %rhs:fpr128 = COPY $q1
; CHECK: %fcmp:fpr128 = nofpexcept FCMGTv2f64 %lhs, %rhs
; CHECK: $q0 = COPY %fcmp
; CHECK: RET_ReallyLR implicit $q0
%lhs:fpr(<2 x s64>) = COPY $q0
%rhs:fpr(<2 x s64>) = COPY $q1
%fcmp:fpr(<2 x s64>) = G_FCMGT %lhs, %rhs(<2 x s64>)
$q0 = COPY %fcmp(<2 x s64>)
RET_ReallyLR implicit $q0
...
---
name: fcmeqz
alignment: 4
legalized: true
regBankSelected: true
body: |
bb.0:
; CHECK-LABEL: name: fcmeqz
; CHECK: %lhs:fpr128 = COPY $q0
; CHECK: %fcmp:fpr128 = nofpexcept FCMEQv2i64rz %lhs
; CHECK: $q0 = COPY %fcmp
; CHECK: RET_ReallyLR implicit $q0
%lhs:fpr(<2 x s64>) = COPY $q0
%zero:gpr(s64) = G_CONSTANT i64 0
%zero_vec:fpr(<2 x s64>) = G_BUILD_VECTOR %zero(s64), %zero(s64)
%fcmp:fpr(<2 x s64>) = G_FCMEQZ %lhs
$q0 = COPY %fcmp(<2 x s64>)
RET_ReallyLR implicit $q0
...
---
name: fcmgez
alignment: 4
legalized: true
regBankSelected: true
body: |
bb.0:
; CHECK-LABEL: name: fcmgez
; CHECK: %lhs:fpr128 = COPY $q0
; CHECK: %fcmp:fpr128 = nofpexcept FCMGEv2i64rz %lhs
; CHECK: $q0 = COPY %fcmp
; CHECK: RET_ReallyLR implicit $q0
%lhs:fpr(<2 x s64>) = COPY $q0
%zero:gpr(s64) = G_CONSTANT i64 0
%zero_vec:fpr(<2 x s64>) = G_BUILD_VECTOR %zero(s64), %zero(s64)
%fcmp:fpr(<2 x s64>) = G_FCMGEZ %lhs
$q0 = COPY %fcmp(<2 x s64>)
RET_ReallyLR implicit $q0
...
---
name: fcmgtz
alignment: 4
legalized: true
regBankSelected: true
body: |
bb.0:
; CHECK-LABEL: name: fcmgtz
; CHECK: %lhs:fpr128 = COPY $q0
; CHECK: %fcmp:fpr128 = nofpexcept FCMGTv2i64rz %lhs
; CHECK: $q0 = COPY %fcmp
; CHECK: RET_ReallyLR implicit $q0
%lhs:fpr(<2 x s64>) = COPY $q0
%zero:gpr(s64) = G_CONSTANT i64 0
%zero_vec:fpr(<2 x s64>) = G_BUILD_VECTOR %zero(s64), %zero(s64)
%fcmp:fpr(<2 x s64>) = G_FCMGTZ %lhs
$q0 = COPY %fcmp(<2 x s64>)
RET_ReallyLR implicit $q0
...
---
name: fcmlez
alignment: 4
legalized: true
regBankSelected: true
body: |
bb.0:
; CHECK-LABEL: name: fcmlez
; CHECK: %lhs:fpr128 = COPY $q0
; CHECK: %fcmp:fpr128 = nofpexcept FCMLEv2i64rz %lhs
; CHECK: $q0 = COPY %fcmp
; CHECK: RET_ReallyLR implicit $q0
%lhs:fpr(<2 x s64>) = COPY $q0
%zero:gpr(s64) = G_CONSTANT i64 0
%zero_vec:fpr(<2 x s64>) = G_BUILD_VECTOR %zero(s64), %zero(s64)
%fcmp:fpr(<2 x s64>) = G_FCMLEZ %lhs
$q0 = COPY %fcmp(<2 x s64>)
RET_ReallyLR implicit $q0
...
---
name: fcmltz
alignment: 4
legalized: true
regBankSelected: true
body: |
bb.0:
; CHECK-LABEL: name: fcmltz
; CHECK: %lhs:fpr128 = COPY $q0
; CHECK: %fcmp:fpr128 = nofpexcept FCMLTv2i64rz %lhs
; CHECK: $q0 = COPY %fcmp
; CHECK: RET_ReallyLR implicit $q0
%lhs:fpr(<2 x s64>) = COPY $q0
%zero:gpr(s64) = G_CONSTANT i64 0
%zero_vec:fpr(<2 x s64>) = G_BUILD_VECTOR %zero(s64), %zero(s64)
%fcmp:fpr(<2 x s64>) = G_FCMLTZ %lhs
$q0 = COPY %fcmp(<2 x s64>)
RET_ReallyLR implicit $q0
|
