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|
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=legalizer %s -o - | FileCheck %s
---
name: test_flog_s32
body: |
bb.0:
liveins: $vgpr0
; CHECK-LABEL: name: test_flog_s32
; CHECK: liveins: $vgpr0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3810000000000000
; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[COPY]](s32), [[C]]
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41F0000000000000
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00
; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C1]], [[C2]]
; CHECK-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[COPY]], [[SELECT]]
; CHECK-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL]](s32)
; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3FE62E42E0000000
; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3E6EFA39E0000000
; CHECK-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[INT]], [[C3]]
; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[FMUL1]]
; CHECK-NEXT: [[FMA:%[0-9]+]]:_(s32) = G_FMA [[INT]], [[C3]], [[FNEG]]
; CHECK-NEXT: [[FMA1:%[0-9]+]]:_(s32) = G_FMA [[INT]], [[C4]], [[FMA]]
; CHECK-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[FMUL1]], [[FMA1]]
; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x7FF0000000000000
; CHECK-NEXT: [[FABS:%[0-9]+]]:_(s32) = G_FABS [[INT]]
; CHECK-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[FABS]](s32), [[C5]]
; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[FCMP1]](s1), [[FADD]], [[INT]]
; CHECK-NEXT: [[C6:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
; CHECK-NEXT: [[C7:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x40362E4300000000
; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C7]], [[C6]]
; CHECK-NEXT: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[SELECT1]], [[SELECT2]]
; CHECK-NEXT: $vgpr0 = COPY [[FSUB]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = G_FLOG %0
$vgpr0 = COPY %1
...
---
name: test_flog_s32_flags
body: |
bb.0:
liveins: $vgpr0
; CHECK-LABEL: name: test_flog_s32_flags
; CHECK: liveins: $vgpr0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3810000000000000
; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[COPY]](s32), [[C]]
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41F0000000000000
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00
; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = nnan G_SELECT [[FCMP]](s1), [[C1]], [[C2]]
; CHECK-NEXT: [[FMUL:%[0-9]+]]:_(s32) = nnan G_FMUL [[COPY]], [[SELECT]]
; CHECK-NEXT: [[INT:%[0-9]+]]:_(s32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL]](s32)
; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3FE62E42E0000000
; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3E6EFA39E0000000
; CHECK-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = nnan G_FMUL [[INT]], [[C3]]
; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s32) = nnan G_FNEG [[FMUL1]]
; CHECK-NEXT: [[FMA:%[0-9]+]]:_(s32) = nnan G_FMA [[INT]], [[C3]], [[FNEG]]
; CHECK-NEXT: [[FMA1:%[0-9]+]]:_(s32) = nnan G_FMA [[INT]], [[C4]], [[FMA]]
; CHECK-NEXT: [[FADD:%[0-9]+]]:_(s32) = nnan G_FADD [[FMUL1]], [[FMA1]]
; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x7FF0000000000000
; CHECK-NEXT: [[FABS:%[0-9]+]]:_(s32) = G_FABS [[INT]]
; CHECK-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = nnan G_FCMP floatpred(olt), [[FABS]](s32), [[C5]]
; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = nnan G_SELECT [[FCMP1]](s1), [[FADD]], [[INT]]
; CHECK-NEXT: [[C6:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
; CHECK-NEXT: [[C7:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x40362E4300000000
; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(s32) = nnan G_SELECT [[FCMP]](s1), [[C7]], [[C6]]
; CHECK-NEXT: [[FSUB:%[0-9]+]]:_(s32) = nnan G_FSUB [[SELECT1]], [[SELECT2]]
; CHECK-NEXT: $vgpr0 = COPY [[FSUB]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = nnan G_FLOG %0
$vgpr0 = COPY %1
...
---
name: test_flog_v2s32
body: |
bb.0:
liveins: $vgpr0_vgpr1
; CHECK-LABEL: name: test_flog_v2s32
; CHECK: liveins: $vgpr0_vgpr1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3810000000000000
; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV]](s32), [[C]]
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41F0000000000000
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00
; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C1]], [[C2]]
; CHECK-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[UV]], [[SELECT]]
; CHECK-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL]](s32)
; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3FE62E42E0000000
; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3E6EFA39E0000000
; CHECK-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[INT]], [[C3]]
; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[FMUL1]]
; CHECK-NEXT: [[FMA:%[0-9]+]]:_(s32) = G_FMA [[INT]], [[C3]], [[FNEG]]
; CHECK-NEXT: [[FMA1:%[0-9]+]]:_(s32) = G_FMA [[INT]], [[C4]], [[FMA]]
; CHECK-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[FMUL1]], [[FMA1]]
; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x7FF0000000000000
; CHECK-NEXT: [[FABS:%[0-9]+]]:_(s32) = G_FABS [[INT]]
; CHECK-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[FABS]](s32), [[C5]]
; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[FCMP1]](s1), [[FADD]], [[INT]]
; CHECK-NEXT: [[C6:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
; CHECK-NEXT: [[C7:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x40362E4300000000
; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C7]], [[C6]]
; CHECK-NEXT: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[SELECT1]], [[SELECT2]]
; CHECK-NEXT: [[FCMP2:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV1]](s32), [[C]]
; CHECK-NEXT: [[SELECT3:%[0-9]+]]:_(s32) = G_SELECT [[FCMP2]](s1), [[C1]], [[C2]]
; CHECK-NEXT: [[FMUL2:%[0-9]+]]:_(s32) = G_FMUL [[UV1]], [[SELECT3]]
; CHECK-NEXT: [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL2]](s32)
; CHECK-NEXT: [[FMUL3:%[0-9]+]]:_(s32) = G_FMUL [[INT1]], [[C3]]
; CHECK-NEXT: [[FNEG1:%[0-9]+]]:_(s32) = G_FNEG [[FMUL3]]
; CHECK-NEXT: [[FMA2:%[0-9]+]]:_(s32) = G_FMA [[INT1]], [[C3]], [[FNEG1]]
; CHECK-NEXT: [[FMA3:%[0-9]+]]:_(s32) = G_FMA [[INT1]], [[C4]], [[FMA2]]
; CHECK-NEXT: [[FADD1:%[0-9]+]]:_(s32) = G_FADD [[FMUL3]], [[FMA3]]
; CHECK-NEXT: [[FABS1:%[0-9]+]]:_(s32) = G_FABS [[INT1]]
; CHECK-NEXT: [[FCMP3:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[FABS1]](s32), [[C5]]
; CHECK-NEXT: [[SELECT4:%[0-9]+]]:_(s32) = G_SELECT [[FCMP3]](s1), [[FADD1]], [[INT1]]
; CHECK-NEXT: [[SELECT5:%[0-9]+]]:_(s32) = G_SELECT [[FCMP2]](s1), [[C7]], [[C6]]
; CHECK-NEXT: [[FSUB1:%[0-9]+]]:_(s32) = G_FSUB [[SELECT4]], [[SELECT5]]
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[FSUB]](s32), [[FSUB1]](s32)
; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
%0:_(<2 x s32>) = COPY $vgpr0_vgpr1
%1:_(<2 x s32>) = G_FLOG %0
$vgpr0_vgpr1 = COPY %1
...
---
name: test_flog_v3s32
body: |
bb.0:
liveins: $vgpr0_vgpr1_vgpr2
; CHECK-LABEL: name: test_flog_v3s32
; CHECK: liveins: $vgpr0_vgpr1_vgpr2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<3 x s32>)
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3810000000000000
; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV]](s32), [[C]]
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41F0000000000000
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00
; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C1]], [[C2]]
; CHECK-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[UV]], [[SELECT]]
; CHECK-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL]](s32)
; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3FE62E42E0000000
; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3E6EFA39E0000000
; CHECK-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[INT]], [[C3]]
; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[FMUL1]]
; CHECK-NEXT: [[FMA:%[0-9]+]]:_(s32) = G_FMA [[INT]], [[C3]], [[FNEG]]
; CHECK-NEXT: [[FMA1:%[0-9]+]]:_(s32) = G_FMA [[INT]], [[C4]], [[FMA]]
; CHECK-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[FMUL1]], [[FMA1]]
; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x7FF0000000000000
; CHECK-NEXT: [[FABS:%[0-9]+]]:_(s32) = G_FABS [[INT]]
; CHECK-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[FABS]](s32), [[C5]]
; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[FCMP1]](s1), [[FADD]], [[INT]]
; CHECK-NEXT: [[C6:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
; CHECK-NEXT: [[C7:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x40362E4300000000
; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C7]], [[C6]]
; CHECK-NEXT: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[SELECT1]], [[SELECT2]]
; CHECK-NEXT: [[FCMP2:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV1]](s32), [[C]]
; CHECK-NEXT: [[SELECT3:%[0-9]+]]:_(s32) = G_SELECT [[FCMP2]](s1), [[C1]], [[C2]]
; CHECK-NEXT: [[FMUL2:%[0-9]+]]:_(s32) = G_FMUL [[UV1]], [[SELECT3]]
; CHECK-NEXT: [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL2]](s32)
; CHECK-NEXT: [[FMUL3:%[0-9]+]]:_(s32) = G_FMUL [[INT1]], [[C3]]
; CHECK-NEXT: [[FNEG1:%[0-9]+]]:_(s32) = G_FNEG [[FMUL3]]
; CHECK-NEXT: [[FMA2:%[0-9]+]]:_(s32) = G_FMA [[INT1]], [[C3]], [[FNEG1]]
; CHECK-NEXT: [[FMA3:%[0-9]+]]:_(s32) = G_FMA [[INT1]], [[C4]], [[FMA2]]
; CHECK-NEXT: [[FADD1:%[0-9]+]]:_(s32) = G_FADD [[FMUL3]], [[FMA3]]
; CHECK-NEXT: [[FABS1:%[0-9]+]]:_(s32) = G_FABS [[INT1]]
; CHECK-NEXT: [[FCMP3:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[FABS1]](s32), [[C5]]
; CHECK-NEXT: [[SELECT4:%[0-9]+]]:_(s32) = G_SELECT [[FCMP3]](s1), [[FADD1]], [[INT1]]
; CHECK-NEXT: [[SELECT5:%[0-9]+]]:_(s32) = G_SELECT [[FCMP2]](s1), [[C7]], [[C6]]
; CHECK-NEXT: [[FSUB1:%[0-9]+]]:_(s32) = G_FSUB [[SELECT4]], [[SELECT5]]
; CHECK-NEXT: [[FCMP4:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV2]](s32), [[C]]
; CHECK-NEXT: [[SELECT6:%[0-9]+]]:_(s32) = G_SELECT [[FCMP4]](s1), [[C1]], [[C2]]
; CHECK-NEXT: [[FMUL4:%[0-9]+]]:_(s32) = G_FMUL [[UV2]], [[SELECT6]]
; CHECK-NEXT: [[INT2:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL4]](s32)
; CHECK-NEXT: [[FMUL5:%[0-9]+]]:_(s32) = G_FMUL [[INT2]], [[C3]]
; CHECK-NEXT: [[FNEG2:%[0-9]+]]:_(s32) = G_FNEG [[FMUL5]]
; CHECK-NEXT: [[FMA4:%[0-9]+]]:_(s32) = G_FMA [[INT2]], [[C3]], [[FNEG2]]
; CHECK-NEXT: [[FMA5:%[0-9]+]]:_(s32) = G_FMA [[INT2]], [[C4]], [[FMA4]]
; CHECK-NEXT: [[FADD2:%[0-9]+]]:_(s32) = G_FADD [[FMUL5]], [[FMA5]]
; CHECK-NEXT: [[FABS2:%[0-9]+]]:_(s32) = G_FABS [[INT2]]
; CHECK-NEXT: [[FCMP5:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[FABS2]](s32), [[C5]]
; CHECK-NEXT: [[SELECT7:%[0-9]+]]:_(s32) = G_SELECT [[FCMP5]](s1), [[FADD2]], [[INT2]]
; CHECK-NEXT: [[SELECT8:%[0-9]+]]:_(s32) = G_SELECT [[FCMP4]](s1), [[C7]], [[C6]]
; CHECK-NEXT: [[FSUB2:%[0-9]+]]:_(s32) = G_FSUB [[SELECT7]], [[SELECT8]]
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[FSUB]](s32), [[FSUB1]](s32), [[FSUB2]](s32)
; CHECK-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
%0:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
%1:_(<3 x s32>) = G_FLOG %0
$vgpr0_vgpr1_vgpr2 = COPY %1
...
---
name: test_flog_s16
body: |
bb.0:
liveins: $vgpr0
; CHECK-LABEL: name: test_flog_s16
; CHECK: liveins: $vgpr0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; CHECK-NEXT: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16)
; CHECK-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FPEXT]](s32)
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3FE62E4300000000
; CHECK-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[INT]], [[C]]
; CHECK-NEXT: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[FMUL]](s32)
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FPTRUNC]](s16)
; CHECK-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s16) = G_TRUNC %0
%2:_(s16) = G_FLOG %1
%3:_(s32) = G_ANYEXT %2
$vgpr0 = COPY %3
...
---
name: test_flog_v2s16
body: |
bb.0:
liveins: $vgpr0
; CHECK-LABEL: name: test_flog_v2s16
; CHECK: liveins: $vgpr0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>)
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](s32)
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
; CHECK-NEXT: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16)
; CHECK-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FPEXT]](s32)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3FE62E4300000000
; CHECK-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[INT]], [[C1]]
; CHECK-NEXT: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[FMUL]](s32)
; CHECK-NEXT: [[FPEXT1:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC1]](s16)
; CHECK-NEXT: [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FPEXT1]](s32)
; CHECK-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[INT1]], [[C1]]
; CHECK-NEXT: [[FPTRUNC1:%[0-9]+]]:_(s16) = G_FPTRUNC [[FMUL1]](s32)
; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[FPTRUNC]](s16)
; CHECK-NEXT: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[FPTRUNC1]](s16)
; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C]](s32)
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL]]
; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; CHECK-NEXT: $vgpr0 = COPY [[BITCAST1]](<2 x s16>)
%0:_(<2 x s16>) = COPY $vgpr0
%1:_(<2 x s16>) = G_FLOG %0
$vgpr0 = COPY %1
...
|
