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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect -regbankselect-greedy -o - %s | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect -regbankselect-fast -o - %s | FileCheck %s
# TODO: We could use scalar
---
name: amdgpu_wave_address
legalized: true
body: |
bb.0:
; CHECK-LABEL: name: amdgpu_wave_address
; CHECK: [[AMDGPU_WAVE_ADDRESS:%[0-9]+]]:vgpr(p5) = G_AMDGPU_WAVE_ADDRESS $sgpr32
; CHECK-NEXT: S_ENDPGM 0, implicit [[AMDGPU_WAVE_ADDRESS]](p5)
%0:_(p5) = G_AMDGPU_WAVE_ADDRESS $sgpr32
S_ENDPGM 0, implicit %0
...
# TODO: Should infer v here
---
name: amdgpu_wave_address_v
legalized: true
body: |
bb.0:
; CHECK-LABEL: name: amdgpu_wave_address_v
; CHECK: [[DEF:%[0-9]+]]:sgpr(p1) = G_IMPLICIT_DEF
; CHECK-NEXT: [[AMDGPU_WAVE_ADDRESS:%[0-9]+]]:vgpr(p5) = G_AMDGPU_WAVE_ADDRESS $sgpr32
; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(p1) = COPY [[DEF]](p1)
; CHECK-NEXT: G_STORE [[AMDGPU_WAVE_ADDRESS]](p5), [[COPY]](p1) :: (store (p5), addrspace 1)
%0:_(p1) = G_IMPLICIT_DEF
%1:_(p5) = G_AMDGPU_WAVE_ADDRESS $sgpr32
G_STORE %1, %0 :: (store (p5), addrspace 1)
...
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