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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -sgpr-regalloc=fast -start-before=regallocfast,0 -stop-before=greedy -o - %s | FileCheck %s
# RegAllocFast was incorrectly dropping subregister indexes on
# unassigned virtual registers. Make sure they are passed through
# undisturbed to the second regalloc run.
---
name: func
alignment: 1
tracksRegLiveness: true
machineFunctionInfo:
scratchRSrcReg: '$sgpr96_sgpr97_sgpr98_sgpr99'
stackPtrOffsetReg: '$sgpr32'
body: |
bb.0:
liveins: $vgpr0, $vgpr1_vgpr2
; CHECK-LABEL: name: func
; CHECK: liveins: $vgpr0, $vgpr1_vgpr2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: undef %0.sub0:vreg_64 = COPY $vgpr0
; CHECK-NEXT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr1_vgpr2
; CHECK-NEXT: undef %2.sub1:vreg_64 = V_MOV_B32_e32 0, implicit $exec
; CHECK-NEXT: undef %0.sub0:vreg_64, renamable $sgpr0_sgpr1 = V_ADD_CO_U32_e64 1, %0.sub0, 0, implicit $exec
; CHECK-NEXT: undef %2.sub1:vreg_64, dead renamable $sgpr0_sgpr1 = V_ADDC_U32_e64 0, %2.sub1, killed $sgpr0_sgpr1, 0, implicit $exec
; CHECK-NEXT: [[GLOBAL_LOAD_DWORDX2_:%[0-9]+]]:vreg_64 = GLOBAL_LOAD_DWORDX2 [[COPY]], 0, 0, implicit $exec
; CHECK-NEXT: $vgpr0 = V_MOV_B32_e32 [[GLOBAL_LOAD_DWORDX2_]].sub0, implicit $exec
; CHECK-NEXT: S_ENDPGM 0, implicit %0, implicit %2, implicit $vgpr0
undef %0.sub0:vreg_64 = COPY $vgpr0
%2:vreg_64 = COPY $vgpr1_vgpr2
undef %1.sub1:vreg_64 = V_MOV_B32_e32 0, implicit $exec
undef %0.sub0:vreg_64, %3:sreg_64_xexec = V_ADD_CO_U32_e64 1, %0.sub0, 0, implicit $exec
undef %1.sub1:vreg_64, dead %4:sreg_64_xexec = V_ADDC_U32_e64 0, %1.sub1, %3, 0, implicit $exec
%5:vreg_64 = GLOBAL_LOAD_DWORDX2 %2, 0, 0, implicit $exec
$vgpr0 = V_MOV_B32_e32 %5.sub0, implicit $exec
S_ENDPGM 0, implicit %0, implicit %1, implicit $vgpr0
...
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