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|
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=arm-- -run-pass=machine-outliner -verify-machineinstrs \
# RUN: %s -o - | FileCheck %s
--- |
define void @outline_cpsr_r12_ok() #0 { ret void }
define void @dont_outline_cpsr_r12_1() #0 { ret void }
define void @dont_outline_cpsr_r12_2() #0 { ret void }
declare void @z(i32, i32, i32, i32)
attributes #0 = { minsize optsize }
...
---
name: outline_cpsr_r12_ok
tracksRegLiveness: true
body: |
; CHECK-LABEL: name: outline_cpsr_r12_ok
; CHECK: bb.0:
; CHECK: BL @OUTLINED_FUNCTION_0
; CHECK: $r3 = MOVr $r12, 14 /* CC::al */, $noreg, $noreg
; CHECK: bb.1:
; CHECK: BL @OUTLINED_FUNCTION_0
; CHECK: $r4 = MOVr $r12, 14 /* CC::al */, $noreg, $noreg
bb.0:
$r12 = MOVi 1, 14, $noreg, $noreg
CMPri $r12, 42, 14, $noreg, implicit-def $cpsr
$r0 = MOVi 1, 14, $noreg, $noreg
$r1 = MOVi 1, 14, $noreg, $noreg
$r2 = MOVi 1, 14, $noreg, $noreg
$r3 = MOVi 1, 14, $noreg, $noreg
BL @z
$r3 = MOVr $r12, 14, $noreg, $noreg
bb.1:
$r12 = MOVi 1, 14, $noreg, $noreg
CMPri $r12, 42, 14, $noreg, implicit-def $cpsr
$r0 = MOVi 1, 14, $noreg, $noreg
$r1 = MOVi 1, 14, $noreg, $noreg
$r2 = MOVi 1, 14, $noreg, $noreg
$r3 = MOVi 1, 14, $noreg, $noreg
BL @z
$r4 = MOVr $r12, 14, $noreg, $noreg
bb.2:
BX_RET 14, $noreg
...
---
name: dont_outline_cpsr_r12_1
tracksRegLiveness: true
body: |
; CHECK-LABEL: name: dont_outline_cpsr_r12_1
; CHECK: bb.0:
; CHECK: BL @OUTLINED_FUNCTION_1
; CHECK: bb.1:
; CHECK: BL @OUTLINED_FUNCTION_1
; CHECK-LABEL: bb.2:
; CHECK-NOT: BL @OUTLINED_FUNCTION_1
bb.0:
$r0 = MOVi 2, 14, $noreg, $noreg
$r1 = MOVi 2, 14, $noreg, $noreg
$r2 = MOVi 2, 14, $noreg, $noreg
$r3 = MOVi 2, 14, $noreg, $noreg
BL @z
bb.1:
$r0 = MOVi 2, 14, $noreg, $noreg
$r1 = MOVi 2, 14, $noreg, $noreg
$r2 = MOVi 2, 14, $noreg, $noreg
$r3 = MOVi 2, 14, $noreg, $noreg
BL @z
bb.2:
$r12 = MOVi 1, 14, $noreg, $noreg
CMPri $r12, 42, 14, $noreg, implicit-def $cpsr
$r0 = MOVi 2, 14, $noreg, $noreg
$r1 = MOVi 2, 14, $noreg, $noreg
$r2 = MOVi 2, 14, $noreg, $noreg
$r3 = MOVi 2, 14, $noreg, $noreg
BL @z
bb.3:
liveins: $cpsr, $r12
BX_RET 14, $noreg
...
---
name: dont_outline_cpsr_r12_2
tracksRegLiveness: true
body: |
; CHECK-LABEL: name: dont_outline_cpsr_r12_2
; CHECK-NOT: BL @OUTLINED_FUNCTION
bb.0:
liveins: $r12
CMPri $r12, 42, 14, $noreg, implicit-def $cpsr
$r0 = MOVi 3, 14, $noreg, $noreg
$r1 = MOVi 3, 14, $noreg, $noreg
$r2 = MOVi 3, 14, $noreg, $noreg
$r3 = MOVi 3, 14, $noreg, $noreg
BL @z
bb.1:
liveins: $r12
CMPri $r12, 42, 14, $noreg, implicit-def $cpsr
$r0 = MOVi 3, 14, $noreg, $noreg
$r1 = MOVi 3, 14, $noreg, $noreg
$r2 = MOVi 3, 14, $noreg, $noreg
$r3 = MOVi 3, 14, $noreg, $noreg
BL @z
bb.2:
liveins: $r12
CMPri $r12, 42, 14, $noreg, implicit-def $cpsr
$r0 = MOVi 3, 14, $noreg, $noreg
$r1 = MOVi 3, 14, $noreg, $noreg
$r2 = MOVi 3, 14, $noreg, $noreg
$r3 = MOVi 3, 14, $noreg, $noreg
BL @z
bb.3:
BX_RET 14, $noreg
|
