File: subregister-operands.mir

package info (click to toggle)
swiftlang 6.0.3-2
  • links: PTS, VCS
  • area: main
  • in suites: trixie
  • size: 2,519,992 kB
  • sloc: cpp: 9,107,863; ansic: 2,040,022; asm: 1,135,751; python: 296,500; objc: 82,456; f90: 60,502; lisp: 34,951; pascal: 19,946; sh: 18,133; perl: 7,482; ml: 4,937; javascript: 4,117; makefile: 3,840; awk: 3,535; xml: 914; fortran: 619; cs: 573; ruby: 573
file content (37 lines) | stat: -rw-r--r-- 909 bytes parent folder | download | duplicates (14) 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
 
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s
# This test ensures that the MIR parser parses subregisters in register operands
# correctly.

--- |

  define zeroext i1 @t(i1 %c) {
  entry:
    ret i1 %c
  }

...
---
name:            t
tracksRegLiveness: true
registers:
  - { id: 0, class: gr32 }
  - { id: 1, class: gr8 }
  - { id: 2, class: gr8 }
body: |
  bb.0.entry:
    liveins: $edi
    ; CHECK-LABEL: name: t
    ; CHECK: liveins: $edi
    ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi
    ; CHECK: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit
    ; CHECK: [[AND8ri:%[0-9]+]]:gr8 = AND8ri [[COPY1]], 1, implicit-def $eflags
    ; CHECK: $al = COPY [[AND8ri]]
    ; CHECK: RET64 $al
    %0 = COPY $edi
    %1 = COPY %0.sub_8bit
    %2 = AND8ri %1, 1, implicit-def $eflags
    $al = COPY %2
    RET64 $al
...