1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
|
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=mipsel-linux-gnu -mcpu=mips32r5 -mattr=+msa,+fp64,+nan2008 -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=P5600
--- |
define void @sqrt_v4f32(ptr %a, ptr %c) { entry: ret void }
define void @sqrt_v2f64(ptr %a, ptr %c) { entry: ret void }
...
---
name: sqrt_v4f32
alignment: 4
legalized: true
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $a0, $a1
; P5600-LABEL: name: sqrt_v4f32
; P5600: liveins: $a0, $a1
; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $a1
; P5600: [[LOAD:%[0-9]+]]:fprb(<4 x s32>) = G_LOAD [[COPY]](p0) :: (load (<4 x s32>) from %ir.a)
; P5600: [[FSQRT:%[0-9]+]]:fprb(<4 x s32>) = G_FSQRT [[LOAD]]
; P5600: G_STORE [[FSQRT]](<4 x s32>), [[COPY1]](p0) :: (store (<4 x s32>) into %ir.c)
; P5600: RetRA
%0:_(p0) = COPY $a0
%1:_(p0) = COPY $a1
%2:_(<4 x s32>) = G_LOAD %0(p0) :: (load (<4 x s32>) from %ir.a)
%3:_(<4 x s32>) = G_FSQRT %2
G_STORE %3(<4 x s32>), %1(p0) :: (store (<4 x s32>) into %ir.c)
RetRA
...
---
name: sqrt_v2f64
alignment: 4
legalized: true
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $a0, $a1
; P5600-LABEL: name: sqrt_v2f64
; P5600: liveins: $a0, $a1
; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $a1
; P5600: [[LOAD:%[0-9]+]]:fprb(<2 x s64>) = G_LOAD [[COPY]](p0) :: (load (<2 x s64>) from %ir.a)
; P5600: [[FSQRT:%[0-9]+]]:fprb(<2 x s64>) = G_FSQRT [[LOAD]]
; P5600: G_STORE [[FSQRT]](<2 x s64>), [[COPY1]](p0) :: (store (<2 x s64>) into %ir.c)
; P5600: RetRA
%0:_(p0) = COPY $a0
%1:_(p0) = COPY $a1
%2:_(<2 x s64>) = G_LOAD %0(p0) :: (load (<2 x s64>) from %ir.a)
%3:_(<2 x s64>) = G_FSQRT %2
G_STORE %3(<2 x s64>), %1(p0) :: (store (<2 x s64>) into %ir.c)
RetRA
...
|
