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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s
; RUN: llc -mtriple=riscv64 -mattr=+v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s
; RUN: llc -mtriple=riscv32 -mattr=+v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s
; RUN: llc -mtriple=riscv64 -mattr=+v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s
define void @load_store_v1i1(ptr %x, ptr %y) {
; CHECK-LABEL: load_store_v1i1:
; CHECK: # %bb.0:
; CHECK-NEXT: lbu a0, 0(a0)
; CHECK-NEXT: andi a0, a0, 1
; CHECK-NEXT: sb a0, 0(a1)
; CHECK-NEXT: ret
%a = load <1 x i1>, ptr %x
store <1 x i1> %a, ptr %y
ret void
}
define void @load_store_v2i1(ptr %x, ptr %y) {
; CHECK-LABEL: load_store_v2i1:
; CHECK: # %bb.0:
; CHECK-NEXT: lbu a0, 0(a0)
; CHECK-NEXT: andi a0, a0, 3
; CHECK-NEXT: sb a0, 0(a1)
; CHECK-NEXT: ret
%a = load <2 x i1>, ptr %x
store <2 x i1> %a, ptr %y
ret void
}
define void @load_store_v4i1(ptr %x, ptr %y) {
; CHECK-LABEL: load_store_v4i1:
; CHECK: # %bb.0:
; CHECK-NEXT: lbu a0, 0(a0)
; CHECK-NEXT: andi a0, a0, 15
; CHECK-NEXT: sb a0, 0(a1)
; CHECK-NEXT: ret
%a = load <4 x i1>, ptr %x
store <4 x i1> %a, ptr %y
ret void
}
define void @load_store_v8i1(ptr %x, ptr %y) {
; CHECK-LABEL: load_store_v8i1:
; CHECK: # %bb.0:
; CHECK-NEXT: lbu a0, 0(a0)
; CHECK-NEXT: sb a0, 0(a1)
; CHECK-NEXT: ret
%a = load <8 x i1>, ptr %x
store <8 x i1> %a, ptr %y
ret void
}
define void @load_store_v16i1(ptr %x, ptr %y) {
; CHECK-LABEL: load_store_v16i1:
; CHECK: # %bb.0:
; CHECK-NEXT: lh a0, 0(a0)
; CHECK-NEXT: sh a0, 0(a1)
; CHECK-NEXT: ret
%a = load <16 x i1>, ptr %x
store <16 x i1> %a, ptr %y
ret void
}
define void @load_store_v32i1(ptr %x, ptr %y) {
; CHECK-LABEL: load_store_v32i1:
; CHECK: # %bb.0:
; CHECK-NEXT: lw a0, 0(a0)
; CHECK-NEXT: sw a0, 0(a1)
; CHECK-NEXT: ret
%a = load <32 x i1>, ptr %x
store <32 x i1> %a, ptr %y
ret void
}
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