1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
|
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=x86_64-linux-gnu -run-pass=legalizer %s -o - | FileCheck %s --check-prefixes=CHECK,X64
# RUN: llc -mtriple=i386-linux-gnu -run-pass=legalizer %s -o - | FileCheck %s --check-prefixes=CHECK,X86
--- |
define void @test_gep_i8c(ptr %addr) {
%arrayidx = getelementptr i32, ptr undef, i8 5
ret void
}
define void @test_gep_i8(ptr %addr, i8 %ofs) {
%arrayidx = getelementptr i32, ptr undef, i8 %ofs
ret void
}
define void @test_gep_i16c(ptr %addr) {
%arrayidx = getelementptr i32, ptr undef, i16 5
ret void
}
define void @test_gep_i16(ptr %addr, i16 %ofs) {
%arrayidx = getelementptr i32, ptr undef, i16 %ofs
ret void
}
define void @test_gep_i32c(ptr %addr) {
%arrayidx = getelementptr i32, ptr undef, i32 5
ret void
}
define void @test_gep_i32(ptr %addr, i32 %ofs) {
%arrayidx = getelementptr i32, ptr undef, i32 %ofs
ret void
}
define void @test_gep_i64c(ptr %addr) {
%arrayidx = getelementptr i32, ptr undef, i64 5
ret void
}
define void @test_gep_i64(ptr %addr, i64 %ofs) {
%arrayidx = getelementptr i32, ptr undef, i64 %ofs
ret void
}
...
---
name: test_gep_i8c
legalized: false
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
body: |
bb.1 (%ir-block.0):
; CHECK-LABEL: name: test_gep_i8c
; CHECK: [[DEF:%[0-9]+]]:_(p0) = IMPLICIT_DEF
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[DEF]], [[C]](s32)
; CHECK-NEXT: G_STORE [[PTR_ADD]](p0), [[DEF]](p0) :: (store (p0) into %ir.addr)
; CHECK-NEXT: RET 0
%0(p0) = IMPLICIT_DEF
%1(s8) = G_CONSTANT i8 20
%2(p0) = G_PTR_ADD %0, %1(s8)
G_STORE %2, %0 :: (store (p0) into %ir.addr)
RET 0
...
---
name: test_gep_i8
legalized: false
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
body: |
bb.1 (%ir-block.0):
; CHECK-LABEL: name: test_gep_i8
; CHECK: [[DEF:%[0-9]+]]:_(p0) = IMPLICIT_DEF
; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(s8) = IMPLICIT_DEF
; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[DEF1]](s8)
; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[DEF]], [[SEXT]](s32)
; CHECK-NEXT: G_STORE [[PTR_ADD]](p0), [[DEF]](p0) :: (store (p0) into %ir.addr)
; CHECK-NEXT: RET 0
%0(p0) = IMPLICIT_DEF
%1(s8) = IMPLICIT_DEF
%2(p0) = G_PTR_ADD %0, %1(s8)
G_STORE %2, %0 :: (store (p0) into %ir.addr)
RET 0
...
---
name: test_gep_i16c
legalized: false
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
body: |
bb.1 (%ir-block.0):
; CHECK-LABEL: name: test_gep_i16c
; CHECK: [[DEF:%[0-9]+]]:_(p0) = IMPLICIT_DEF
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[DEF]], [[C]](s32)
; CHECK-NEXT: G_STORE [[PTR_ADD]](p0), [[DEF]](p0) :: (store (p0) into %ir.addr)
; CHECK-NEXT: RET 0
%0(p0) = IMPLICIT_DEF
%1(s16) = G_CONSTANT i16 20
%2(p0) = G_PTR_ADD %0, %1(s16)
G_STORE %2, %0 :: (store (p0) into %ir.addr)
RET 0
...
---
name: test_gep_i16
legalized: false
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
body: |
bb.1 (%ir-block.0):
; CHECK-LABEL: name: test_gep_i16
; CHECK: [[DEF:%[0-9]+]]:_(p0) = IMPLICIT_DEF
; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(s16) = IMPLICIT_DEF
; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[DEF1]](s16)
; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[DEF]], [[SEXT]](s32)
; CHECK-NEXT: G_STORE [[PTR_ADD]](p0), [[DEF]](p0) :: (store (p0) into %ir.addr)
; CHECK-NEXT: RET 0
%0(p0) = IMPLICIT_DEF
%1(s16) = IMPLICIT_DEF
%2(p0) = G_PTR_ADD %0, %1(s16)
G_STORE %2, %0 :: (store (p0) into %ir.addr)
RET 0
...
---
name: test_gep_i32c
legalized: false
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
body: |
bb.1 (%ir-block.0):
; CHECK-LABEL: name: test_gep_i32c
; CHECK: [[DEF:%[0-9]+]]:_(p0) = IMPLICIT_DEF
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[DEF]], [[C]](s32)
; CHECK-NEXT: G_STORE [[PTR_ADD]](p0), [[DEF]](p0) :: (store (p0) into %ir.addr)
; CHECK-NEXT: RET 0
%0(p0) = IMPLICIT_DEF
%1(s32) = G_CONSTANT i32 20
%2(p0) = G_PTR_ADD %0, %1(s32)
G_STORE %2, %0 :: (store (p0) into %ir.addr)
RET 0
...
---
name: test_gep_i32
legalized: false
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
body: |
bb.1 (%ir-block.0):
; CHECK-LABEL: name: test_gep_i32
; CHECK: [[DEF:%[0-9]+]]:_(p0) = IMPLICIT_DEF
; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(s32) = IMPLICIT_DEF
; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[DEF]], [[DEF1]](s32)
; CHECK-NEXT: G_STORE [[PTR_ADD]](p0), [[DEF]](p0) :: (store (p0) into %ir.addr)
; CHECK-NEXT: RET 0
%0(p0) = IMPLICIT_DEF
%1(s32) = IMPLICIT_DEF
%2(p0) = G_PTR_ADD %0, %1(s32)
G_STORE %2, %0 :: (store (p0) into %ir.addr)
RET 0
...
---
name: test_gep_i64c
legalized: false
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
body: |
bb.1 (%ir-block.0):
; X64-LABEL: name: test_gep_i64c
; X64: [[DEF:%[0-9]+]]:_(p0) = IMPLICIT_DEF
; X64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 20
; X64-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[DEF]], [[C]](s64)
; X64-NEXT: G_STORE [[PTR_ADD]](p0), [[DEF]](p0) :: (store (p0) into %ir.addr)
; X64-NEXT: RET 0
; X86-LABEL: name: test_gep_i64c
; X86: [[DEF:%[0-9]+]]:_(p0) = IMPLICIT_DEF
; X86-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
; X86-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[DEF]], [[C]](s32)
; X86-NEXT: G_STORE [[PTR_ADD]](p0), [[DEF]](p0) :: (store (p0) into %ir.addr)
; X86-NEXT: RET 0
%0(p0) = IMPLICIT_DEF
%1(s64) = G_CONSTANT i64 20
%2(p0) = G_PTR_ADD %0, %1(s64)
G_STORE %2, %0 :: (store (p0) into %ir.addr)
RET 0
...
---
name: test_gep_i64
legalized: false
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
body: |
bb.1 (%ir-block.0):
; X64-LABEL: name: test_gep_i64
; X64: [[DEF:%[0-9]+]]:_(p0) = IMPLICIT_DEF
; X64-NEXT: [[DEF1:%[0-9]+]]:_(s64) = IMPLICIT_DEF
; X64-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[DEF]], [[DEF1]](s64)
; X64-NEXT: G_STORE [[PTR_ADD]](p0), [[DEF]](p0) :: (store (p0) into %ir.addr)
; X64-NEXT: RET 0
; X86-LABEL: name: test_gep_i64
; X86: [[DEF:%[0-9]+]]:_(p0) = IMPLICIT_DEF
; X86-NEXT: [[DEF1:%[0-9]+]]:_(s64) = IMPLICIT_DEF
; X86-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[DEF1]](s64)
; X86-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[DEF]], [[TRUNC]](s32)
; X86-NEXT: G_STORE [[PTR_ADD]](p0), [[DEF]](p0) :: (store (p0) into %ir.addr)
; X86-NEXT: RET 0
%0(p0) = IMPLICIT_DEF
%1(s64) = IMPLICIT_DEF
%2(p0) = G_PTR_ADD %0, %1(s64)
G_STORE %2, %0 :: (store (p0) into %ir.addr)
RET 0
...
|
