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|
# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx2 --global-isel -run-pass=regbankselect %s -o - | FileCheck %s
# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx2 --global-isel -regbankselect-greedy -run-pass=regbankselect %s -o - | FileCheck %s
--- |
define void @test_mul_vec256() {
ret void
}
define void @test_add_vec256() {
ret void
}
define void @test_sub_vec256() {
ret void
}
define <8 x i32> @test_load_v8i32_noalign(ptr %p1) {
%r = load <8 x i32>, ptr %p1, align 1
ret <8 x i32> %r
}
define void @test_store_v8i32_noalign(<8 x i32> %val, ptr %p1) {
store <8 x i32> %val, ptr %p1, align 1
ret void
}
---
name: test_mul_vec256
alignment: 16
legalized: true
regBankSelected: false
selected: false
tracksRegLiveness: true
# CHECK-LABEL: name: test_mul_vec256
# CHECK: registers:
# CHECK: - { id: 0, class: vecr, preferred-register: '' }
# CHECK: - { id: 1, class: vecr, preferred-register: '' }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
body: |
bb.1 (%ir-block.0):
%0(<8 x s32>) = IMPLICIT_DEF
%1(<8 x s32>) = G_MUL %0, %0
RET 0
...
---
name: test_add_vec256
alignment: 16
legalized: true
regBankSelected: false
selected: false
tracksRegLiveness: true
# CHECK-LABEL: name: test_add_vec256
# CHECK: registers:
# CHECK: - { id: 0, class: vecr, preferred-register: '' }
# CHECK: - { id: 1, class: vecr, preferred-register: '' }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
body: |
bb.1 (%ir-block.0):
%0(<8 x s32>) = IMPLICIT_DEF
%1(<8 x s32>) = G_ADD %0, %0
RET 0
...
---
name: test_sub_vec256
alignment: 16
legalized: true
regBankSelected: false
selected: false
tracksRegLiveness: true
# CHECK-LABEL: name: test_sub_vec256
# CHECK: registers:
# CHECK: - { id: 0, class: vecr, preferred-register: '' }
# CHECK: - { id: 1, class: vecr, preferred-register: '' }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
body: |
bb.1 (%ir-block.0):
%0(<8 x s32>) = IMPLICIT_DEF
%1(<8 x s32>) = G_SUB %0, %0
RET 0
...
---
name: test_load_v8i32_noalign
# CHECK-LABEL: name: test_load_v8i32_noalign
alignment: 16
legalized: true
regBankSelected: false
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: vecr, preferred-register: '' }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
body: |
bb.1 (%ir-block.0):
liveins: $rdi
%0(p0) = COPY $rdi
%1(<8 x s32>) = G_LOAD %0(p0) :: (load (<8 x s32>) from %ir.p1, align 1)
$ymm0 = COPY %1(<8 x s32>)
RET 0, implicit $ymm0
...
---
name: test_store_v8i32_noalign
# CHECK-LABEL: name: test_store_v8i32_noalign
alignment: 16
legalized: true
regBankSelected: false
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: vecr, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
body: |
bb.1 (%ir-block.0):
liveins: $rdi, $ymm0
%0(<8 x s32>) = COPY $ymm0
%1(p0) = COPY $rdi
G_STORE %0(<8 x s32>), %1(p0) :: (store (<8 x s32>) into %ir.p1, align 1)
RET 0
...
|
