1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
|
// RUN: mlir-opt --split-input-file --verify-diagnostics \
// RUN: --spirv-webgpu-prepare --cse %s | FileCheck %s
//===----------------------------------------------------------------------===//
// spirv.UMulExtended
//===----------------------------------------------------------------------===//
spirv.module Logical GLSL450 {
// CHECK-LABEL: func @umul_extended_i32
// CHECK-SAME: ([[ARG0:%.+]]: i32, [[ARG1:%.+]]: i32)
// CHECK-DAG: [[CSTMASK:%.+]] = spirv.Constant 65535 : i32
// CHECK-DAG: [[CST16:%.+]] = spirv.Constant 16 : i32
// CHECK-NEXT: [[LHSLOW:%.+]] = spirv.BitwiseAnd [[ARG0]], [[CSTMASK]] : i32
// CHECK-NEXT: [[LHSHI:%.+]] = spirv.ShiftRightLogical [[ARG0]], [[CST16]] : i32
// CHECK-NEXT: [[RHSLOW:%.+]] = spirv.BitwiseAnd [[ARG1]], [[CSTMASK]] : i32
// CHECK-NEXT: [[RHSHI:%.+]] = spirv.ShiftRightLogical [[ARG1]], [[CST16]] : i32
// CHECK-DAG: spirv.IMul [[LHSLOW]], [[RHSLOW]]
// CHECK-DAG: spirv.IMul [[LHSLOW]], [[RHSHI]]
// CHECK-DAG: spirv.IMul [[LHSHI]], [[RHSLOW]]
// CHECK-DAG: spirv.IMul [[LHSHI]], [[RHSHI]]
// CHECK-DAG: spirv.IAdd
// CHECK-DAG: spirv.IAdd
// CHECK-DAG: spirv.IAdd
// CHECK-DAG: spirv.IAdd
// CHECK: spirv.ShiftLeftLogical {{%.+}}, [[CST16]] : i32
// CHECK: spirv.BitwiseOr
// CHECK: spirv.ShiftLeftLogical {{%.+}}, [[CST16]] : i32
// CHECK: spirv.BitwiseOr
// CHECK: [[RES:%.+]] = spirv.CompositeConstruct [[RESLO:%.+]], [[RESHI:%.+]] : (i32, i32) -> !spirv.struct<(i32, i32)>
// CHECK-NEXT: spirv.ReturnValue [[RES]] : !spirv.struct<(i32, i32)>
spirv.func @umul_extended_i32(%arg0 : i32, %arg1 : i32) -> !spirv.struct<(i32, i32)> "None" {
%0 = spirv.UMulExtended %arg0, %arg1 : !spirv.struct<(i32, i32)>
spirv.ReturnValue %0 : !spirv.struct<(i32, i32)>
}
// CHECK-LABEL: func @umul_extended_vector_i32
// CHECK-SAME: ([[ARG0:%.+]]: vector<3xi32>, [[ARG1:%.+]]: vector<3xi32>)
// CHECK-DAG: [[CSTMASK:%.+]] = spirv.Constant dense<65535> : vector<3xi32>
// CHECK-DAG: [[CST16:%.+]] = spirv.Constant dense<16> : vector<3xi32>
// CHECK-NEXT: [[LHSLOW:%.+]] = spirv.BitwiseAnd [[ARG0]], [[CSTMASK]] : vector<3xi32>
// CHECK-NEXT: [[LHSHI:%.+]] = spirv.ShiftRightLogical [[ARG0]], [[CST16]] : vector<3xi32>
// CHECK-NEXT: [[RHSLOW:%.+]] = spirv.BitwiseAnd [[ARG1]], [[CSTMASK]] : vector<3xi32>
// CHECK-NEXT: [[RHSHI:%.+]] = spirv.ShiftRightLogical [[ARG1]], [[CST16]] : vector<3xi32>
// CHECK-DAG: spirv.IMul [[LHSLOW]], [[RHSLOW]]
// CHECK-DAG: spirv.IMul [[LHSLOW]], [[RHSHI]]
// CHECK-DAG: spirv.IMul [[LHSHI]], [[RHSLOW]]
// CHECK-DAG: spirv.IMul [[LHSHI]], [[RHSHI]]
// CHECK-DAG: spirv.IAdd
// CHECK-DAG: spirv.IAdd
// CHECK-DAG: spirv.IAdd
// CHECK-DAG: spirv.IAdd
// CHECK: spirv.ShiftLeftLogical {{%.+}}, [[CST16]]
// CHECK: spirv.BitwiseOr
// CHECK: spirv.ShiftLeftLogical {{%.+}}, [[CST16]]
// CHECK: spirv.BitwiseOr
// CHECK-NEXT: [[RES:%.+]] = spirv.CompositeConstruct [[RESLOW:%.+]], [[RESHI:%.+]]
// CHECK-NEXT: spirv.ReturnValue [[RES]] : !spirv.struct<(vector<3xi32>, vector<3xi32>)>
spirv.func @umul_extended_vector_i32(%arg0 : vector<3xi32>, %arg1 : vector<3xi32>)
-> !spirv.struct<(vector<3xi32>, vector<3xi32>)> "None" {
%0 = spirv.UMulExtended %arg0, %arg1 : !spirv.struct<(vector<3xi32>, vector<3xi32>)>
spirv.ReturnValue %0 : !spirv.struct<(vector<3xi32>, vector<3xi32>)>
}
// CHECK-LABEL: func @umul_extended_i16
// CHECK-NEXT: spirv.UMulExtended
// CHECK-NEXT: spirv.ReturnValue
spirv.func @umul_extended_i16(%arg : i16) -> !spirv.struct<(i16, i16)> "None" {
%0 = spirv.UMulExtended %arg, %arg : !spirv.struct<(i16, i16)>
spirv.ReturnValue %0 : !spirv.struct<(i16, i16)>
}
//===----------------------------------------------------------------------===//
// spirv.SMulExtended
//===----------------------------------------------------------------------===//
// CHECK-LABEL: func @smul_extended_i32
// CHECK-SAME: ([[ARG0:%.+]]: i32, [[ARG1:%.+]]: i32)
// CHECK-DAG: [[CSTMASK:%.+]] = spirv.Constant 65535 : i32
// CHECK-DAG: [[CST16:%.+]] = spirv.Constant 16 : i32
// CHECK-NEXT: [[LHSLOW:%.+]] = spirv.BitwiseAnd [[ARG0]], [[CSTMASK]] : i32
// CHECK-NEXT: [[LHSHI:%.+]] = spirv.ShiftRightLogical [[ARG0]], [[CST16]] : i32
// CHECK-NEXT: [[LHSSIGN:%.+]] = spirv.ShiftRightArithmetic [[ARG0]], [[CST16]] : i32
// CHECK-NEXT: [[LHSEXT:%.+]] = spirv.ShiftRightLogical [[LHSSIGN]], [[CST16]] : i32
// CHECK-NEXT: [[RHSLOW:%.+]] = spirv.BitwiseAnd [[ARG1]], [[CSTMASK]] : i32
// CHECK-NEXT: [[RHSHI:%.+]] = spirv.ShiftRightLogical [[ARG1]], [[CST16]] : i32
// CHECK-NEXT: [[RHSSIGN:%.+]] = spirv.ShiftRightArithmetic [[ARG1]], [[CST16]] : i32
// CHECK-NEXT: [[RHSEXT:%.+]] = spirv.ShiftRightLogical [[RHSSIGN]], [[CST16]] : i32
// CHECK-DAG: spirv.IMul [[LHSLOW]], [[RHSLOW]]
// CHECK-DAG: spirv.IMul [[LHSLOW]], [[RHSHI]]
// CHECK-DAG: spirv.IMul [[LHSLOW]], [[RHSEXT]]
// CHECK-DAG: spirv.IMul [[LHSHI]], [[RHSLOW]]
// CHECK-DAG: spirv.IMul [[LHSHI]], [[RHSHI]]
// CHECK-DAG: spirv.IMul [[LHSHI]], [[RHSEXT]]
// CHECK-DAG: spirv.IMul [[LHSEXT]], [[RHSLOW]]
// CHECK-DAG: spirv.IMul [[LHSEXT]], [[RHSHI]]
// CHECK: spirv.ShiftLeftLogical {{%.+}}, [[CST16]] : i32
// CHECK: spirv.BitwiseOr
// CHECK: spirv.ShiftLeftLogical {{%.+}}, [[CST16]] : i32
// CHECK: spirv.BitwiseOr
// CHECK: [[RES:%.+]] = spirv.CompositeConstruct [[RESLO:%.+]], [[RESHI:%.+]] : (i32, i32) -> !spirv.struct<(i32, i32)>
// CHECK-NEXT: spirv.ReturnValue [[RES]] : !spirv.struct<(i32, i32)>
spirv.func @smul_extended_i32(%arg0 : i32, %arg1 : i32) -> !spirv.struct<(i32, i32)> "None" {
%0 = spirv.SMulExtended %arg0, %arg1 : !spirv.struct<(i32, i32)>
spirv.ReturnValue %0 : !spirv.struct<(i32, i32)>
}
// CHECK-LABEL: func @smul_extended_vector_i32
// CHECK-SAME: ([[ARG0:%.+]]: vector<3xi32>, [[ARG1:%.+]]: vector<3xi32>)
// CHECK-DAG: [[CSTMASK:%.+]] = spirv.Constant dense<65535> : vector<3xi32>
// CHECK-DAG: [[CST16:%.+]] = spirv.Constant dense<16> : vector<3xi32>
// CHECK-NEXT: [[LHSLOW:%.+]] = spirv.BitwiseAnd [[ARG0]], [[CSTMASK]] : vector<3xi32>
// CHECK-NEXT: [[LHSHI:%.+]] = spirv.ShiftRightLogical [[ARG0]], [[CST16]] : vector<3xi32>
// CHECK-NEXT: [[LHSSIGN:%.+]] = spirv.ShiftRightArithmetic [[ARG0]], [[CST16]] : vector<3xi32>
// CHECK-NEXT: [[LHSEXT:%.+]] = spirv.ShiftRightLogical [[LHSSIGN]], [[CST16]] : vector<3xi32>
// CHECK-NEXT: [[RHSLOW:%.+]] = spirv.BitwiseAnd [[ARG1]], [[CSTMASK]] : vector<3xi32>
// CHECK-NEXT: [[RHSHI:%.+]] = spirv.ShiftRightLogical [[ARG1]], [[CST16]] : vector<3xi32>
// CHECK-NEXT: [[RHSSIGN:%.+]] = spirv.ShiftRightArithmetic [[ARG1]], [[CST16]] : vector<3xi32>
// CHECK-NEXT: [[RHSEXT:%.+]] = spirv.ShiftRightLogical [[RHSSIGN]], [[CST16]] : vector<3xi32>
// CHECK-DAG: spirv.IMul [[LHSLOW]], [[RHSLOW]]
// CHECK-DAG: spirv.IMul [[LHSLOW]], [[RHSHI]]
// CHECK-DAG: spirv.IMul [[LHSLOW]], [[RHSEXT]]
// CHECK-DAG: spirv.IMul [[LHSHI]], [[RHSLOW]]
// CHECK-DAG: spirv.IMul [[LHSHI]], [[RHSHI]]
// CHECK-DAG: spirv.IMul [[LHSHI]], [[RHSEXT]]
// CHECK-DAG: spirv.IMul [[LHSEXT]], [[RHSLOW]]
// CHECK-DAG: spirv.IMul [[LHSEXT]], [[RHSHI]]
// CHECK: spirv.ShiftLeftLogical {{%.+}}, [[CST16]]
// CHECK: spirv.BitwiseOr
// CHECK: spirv.ShiftLeftLogical {{%.+}}, [[CST16]]
// CHECK: spirv.BitwiseOr
// CHECK-NEXT: [[RES:%.+]] = spirv.CompositeConstruct [[RESLOW:%.+]], [[RESHI:%.+]]
// CHECK-NEXT: spirv.ReturnValue [[RES]] : !spirv.struct<(vector<3xi32>, vector<3xi32>)>
spirv.func @smul_extended_vector_i32(%arg0 : vector<3xi32>, %arg1 : vector<3xi32>)
-> !spirv.struct<(vector<3xi32>, vector<3xi32>)> "None" {
%0 = spirv.SMulExtended %arg0, %arg1 : !spirv.struct<(vector<3xi32>, vector<3xi32>)>
spirv.ReturnValue %0 : !spirv.struct<(vector<3xi32>, vector<3xi32>)>
}
// CHECK-LABEL: func @smul_extended_i16
// CHECK-NEXT: spirv.SMulExtended
// CHECK-NEXT: spirv.ReturnValue
spirv.func @smul_extended_i16(%arg : i16) -> !spirv.struct<(i16, i16)> "None" {
%0 = spirv.SMulExtended %arg, %arg : !spirv.struct<(i16, i16)>
spirv.ReturnValue %0 : !spirv.struct<(i16, i16)>
}
} // end module
|
