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|
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple aarch64-apple-ios -run-pass=aarch64-prelegalizer-combiner %s -o - -verify-machineinstrs | FileCheck %s
---
name: test_rotr
alignment: 4
tracksRegLiveness: true
liveins:
- { reg: '$w0' }
- { reg: '$w1' }
frameInfo:
maxAlignment: 1
machineFunctionInfo: {}
body: |
bb.1.entry:
liveins: $w0, $w1
; CHECK-LABEL: name: test_rotr
; CHECK: liveins: $w0, $w1
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
; CHECK: [[ROTR:%[0-9]+]]:_(s32) = G_ROTR [[COPY]], [[COPY1]](s32)
; CHECK: $w0 = COPY [[ROTR]](s32)
; CHECK: RET_ReallyLR implicit $w0
%0:_(s32) = COPY $w0
%1:_(s32) = COPY $w1
%2:_(s32) = G_FSHR %0, %0, %1(s32)
$w0 = COPY %2(s32)
RET_ReallyLR implicit $w0
...
---
name: test_rotl
alignment: 4
tracksRegLiveness: true
liveins:
- { reg: '$w0' }
- { reg: '$w1' }
frameInfo:
maxAlignment: 1
machineFunctionInfo: {}
body: |
bb.1.entry:
liveins: $w0, $w1
; CHECK-LABEL: name: test_rotl
; CHECK: liveins: $w0, $w1
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
; CHECK: [[ROTL:%[0-9]+]]:_(s32) = G_ROTL [[COPY]], [[COPY1]](s32)
; CHECK: $w0 = COPY [[ROTL]](s32)
; CHECK: RET_ReallyLR implicit $w0
%0:_(s32) = COPY $w0
%1:_(s32) = COPY $w1
%2:_(s32) = G_FSHL %0, %0, %1(s32)
$w0 = COPY %2(s32)
RET_ReallyLR implicit $w0
...
---
name: test_vector_rotr
alignment: 4
tracksRegLiveness: true
liveins:
- { reg: '$w0' }
- { reg: '$w1' }
frameInfo:
maxAlignment: 1
machineFunctionInfo: {}
body: |
bb.1.entry:
liveins: $q0, $q1
; CHECK-LABEL: name: test_vector_rotr
; CHECK: liveins: $q0, $q1
; CHECK: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
; CHECK: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $q1
; CHECK: [[ROTR:%[0-9]+]]:_(<4 x s32>) = G_ROTR [[COPY]], [[COPY1]](<4 x s32>)
; CHECK: $q0 = COPY [[ROTR]](<4 x s32>)
; CHECK: RET_ReallyLR implicit $q0
%0:_(<4 x s32>) = COPY $q0
%1:_(<4 x s32>) = COPY $q1
%2:_(<4 x s32>) = G_FSHR %0, %0, %1(<4 x s32>)
$q0 = COPY %2(<4 x s32>)
RET_ReallyLR implicit $q0
...
---
name: test_vector_rotl
alignment: 4
tracksRegLiveness: true
liveins:
- { reg: '$w0' }
- { reg: '$w1' }
frameInfo:
maxAlignment: 1
machineFunctionInfo: {}
body: |
bb.1.entry:
liveins: $q0, $q1
; CHECK-LABEL: name: test_vector_rotl
; CHECK: liveins: $q0, $q1
; CHECK: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
; CHECK: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $q1
; CHECK: [[ROTL:%[0-9]+]]:_(<4 x s32>) = G_ROTL [[COPY]], [[COPY1]](<4 x s32>)
; CHECK: $q0 = COPY [[ROTL]](<4 x s32>)
; CHECK: RET_ReallyLR implicit $q0
%0:_(<4 x s32>) = COPY $q0
%1:_(<4 x s32>) = COPY $q1
%2:_(<4 x s32>) = G_FSHL %0, %0, %1(<4 x s32>)
$q0 = COPY %2(<4 x s32>)
RET_ReallyLR implicit $q0
...
|
