1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
|
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
--- |
target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
define void @sextload_s32_from_s16(ptr %addr) { ret void }
define void @sextload_s32_from_s16_not_combined(ptr %addr) { ret void }
...
---
name: sextload_s32_from_s16
legalized: true
regBankSelected: true
body: |
bb.0:
liveins: $x0
; CHECK-LABEL: name: sextload_s32_from_s16
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
; CHECK: [[T0:%[0-9]+]]:gpr32 = LDRSHWui [[COPY]], 0 :: (load (s16) from %ir.addr)
; CHECK: $w0 = COPY [[T0]]
%0:gpr(p0) = COPY $x0
%1:gpr(s32) = G_SEXTLOAD %0 :: (load (s16) from %ir.addr)
$w0 = COPY %1(s32)
...
---
name: sextload_s32_from_s16_not_combined
legalized: true
regBankSelected: true
body: |
bb.0:
liveins: $x0
; CHECK-LABEL: name: sextload_s32_from_s16_not_combined
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
; CHECK: [[T0:%[0-9]+]]:gpr32 = LDRHHui [[COPY]], 0 :: (load (s16) from %ir.addr)
; CHECK: [[T1:%[0-9]+]]:gpr32 = SBFMWri [[T0]], 0, 15
; CHECK: $w0 = COPY [[T1]]
%0:gpr(p0) = COPY $x0
%1:gpr(s16) = G_LOAD %0 :: (load (s16) from %ir.addr)
%2:gpr(s32) = G_SEXT %1
$w0 = COPY %2(s32)
...
|
