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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s | FileCheck %s
target triple = "aarch64-unknown-linux-gnu"
;
; ADR
; Tests adr z0.s, [z0.s, z0.s, lsl #<1,2,3>]
; Other formats are tested in llvm/test/CodeGen/AArch64/sve-gep.ll
;
define <vscale x 4 x i32> @adr_32bit_lsl1(<vscale x 4 x i32> %base, <vscale x 4 x i32> %idx) #0 {
; CHECK-LABEL: adr_32bit_lsl1:
; CHECK: // %bb.0:
; CHECK-NEXT: adr z0.s, [z0.s, z1.s, lsl #1]
; CHECK-NEXT: ret
%splat_insert = insertelement <vscale x 4 x i32> poison, i32 1, i32 0
%one = shufflevector <vscale x 4 x i32> %splat_insert, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
%shiftedOffset = shl <vscale x 4 x i32> %idx, %one
%address = add <vscale x 4 x i32> %base, %shiftedOffset
ret <vscale x 4 x i32> %address
}
define <vscale x 4 x i32> @adr_32bit_lsl2(<vscale x 4 x i32> %base, <vscale x 4 x i32> %idx) #0 {
; CHECK-LABEL: adr_32bit_lsl2:
; CHECK: // %bb.0:
; CHECK-NEXT: adr z0.s, [z0.s, z1.s, lsl #2]
; CHECK-NEXT: ret
%splat_insert = insertelement <vscale x 4 x i32> poison, i32 2, i32 0
%two = shufflevector <vscale x 4 x i32> %splat_insert, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
%shiftedOffset = shl <vscale x 4 x i32> %idx, %two
%address = add <vscale x 4 x i32> %base, %shiftedOffset
ret <vscale x 4 x i32> %address
}
define <vscale x 4 x i32> @adr_32bit_lsl3(<vscale x 4 x i32> %base, <vscale x 4 x i32> %idx) #0 {
; CHECK-LABEL: adr_32bit_lsl3:
; CHECK: // %bb.0:
; CHECK-NEXT: adr z0.s, [z0.s, z1.s, lsl #3]
; CHECK-NEXT: ret
%splat_insert = insertelement <vscale x 4 x i32> poison, i32 3, i32 0
%three = shufflevector <vscale x 4 x i32> %splat_insert, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
%shiftedOffset = shl <vscale x 4 x i32> %idx, %three
%address = add <vscale x 4 x i32> %base, %shiftedOffset
ret <vscale x 4 x i32> %address
}
attributes #0 = { "target-features"="+sve" }
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