File: postrasched.ll

package info (click to toggle)
swiftlang 6.1.3-2
  • links: PTS, VCS
  • area: main
  • in suites: forky, sid
  • size: 2,791,604 kB
  • sloc: cpp: 9,901,740; ansic: 2,201,431; asm: 1,091,827; python: 308,252; objc: 82,166; f90: 80,126; lisp: 38,358; pascal: 25,559; sh: 20,429; ml: 5,058; perl: 4,745; makefile: 4,484; awk: 3,535; javascript: 3,018; xml: 918; fortran: 664; cs: 573; ruby: 396
file content (30 lines) | stat: -rw-r--r-- 810 bytes parent folder | download | duplicates (17) 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
 
; REQUIRES: asserts
; RUN: llc < %s -mtriple=thumbv8m.main-none-eabi -debug-only=machine-scheduler,post-RA-sched -print-before=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s

; CHECK-LABEL: test_misched
; Pre and post ra machine scheduling
; CHECK:  ********** MI Scheduling **********
; CHECK:  t2LDRi12
; CHECK:  Latency            : 2
; CHECK:  ********** MI Scheduling **********
; CHECK:  t2LDRi12
; CHECK:  Latency            : 2

define i32 @test_misched(ptr %ptr) "target-cpu"="cortex-m33" {
entry:
  %l = load i32, ptr %ptr
  store i32 0, ptr %ptr
  ret i32 %l
}

; CHECK-LABEL: test_rasched
; CHECK: Subtarget disables post-MI-sched.
; CHECK: ********** List Scheduling **********

define i32 @test_rasched(ptr %ptr) {
entry:
  %l = load i32, ptr %ptr
  store i32 0, ptr %ptr
  ret i32 %l
}