File: isel-op-zext-i1.ll

package info (click to toggle)
swiftlang 6.1.3-2
  • links: PTS, VCS
  • area: main
  • in suites: forky, sid
  • size: 2,791,604 kB
  • sloc: cpp: 9,901,740; ansic: 2,201,431; asm: 1,091,827; python: 308,252; objc: 82,166; f90: 80,126; lisp: 38,358; pascal: 25,559; sh: 20,429; ml: 5,058; perl: 4,745; makefile: 4,484; awk: 3,535; javascript: 3,018; xml: 918; fortran: 664; cs: 573; ruby: 396
file content (13 lines) | stat: -rw-r--r-- 446 bytes parent folder | download | duplicates (26) 
1
2
3
4
5
6
7
8
9
10
11
12
13
 
; RUN: llc -march=hexagon -hexagon-expand-condsets=0 < %s | FileCheck %s

; In the IR, the i1 value is zero-extended first, then passed to add.
; Check that in the final code, the mux happens after the add.
; CHECK: [[REG1:r[0-9]+]] = add([[REG0:r[0-9]+]],#1)
; CHECK: r{{[0-9]+}} = mux(p{{[0-3]}},[[REG1]],[[REG0]])

define i32 @foo(i32 %a, i32 %b) {
  %v0 = icmp eq i32 %a, %b
  %v1 = zext i1 %v0 to i32
  %v2 = add i32 %v1, %a
  ret i32 %v2
}