File: combine.mir

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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
# RUN: llc -run-pass=riscv-prelegalizer-combiner -mtriple riscv64 %s -o - | FileCheck %s --check-prefix=RV64

---
name:            nneg_zext
body:             |
  bb.0:

    ; RV64-LABEL: name: nneg_zext
    ; RV64: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
    ; RV64-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
    ; RV64-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[TRUNC]](s32)
    ; RV64-NEXT: $x10 = COPY [[SEXT]](s64)
    ; RV64-NEXT: PseudoRET implicit $x10
    %0:_(s64) = COPY $x10
    %2:_(s32) = G_TRUNC %0
    %3:_(s64) = nneg G_ZEXT %2
    $x10 = COPY %3(s64)
    PseudoRET implicit $x10
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