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|
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=riscv64 -run-pass=instruction-select -simplify-mir -verify-machineinstrs %s -o - \
# RUN: | FileCheck -check-prefix=RV64I %s
---
name: virt_to_phys
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0.entry:
; RV64I-LABEL: name: virt_to_phys
; RV64I: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 1
; RV64I-NEXT: $x10 = COPY [[ADDI]]
; RV64I-NEXT: PseudoRET implicit $x10
%0:gprb(s64) = G_CONSTANT i64 1
$x10 = COPY %0(s64)
PseudoRET implicit $x10
...
---
name: phys_to_phys
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0.entry:
liveins: $x10, $x11
; RV64I-LABEL: name: phys_to_phys
; RV64I: liveins: $x10, $x11
; RV64I-NEXT: {{ $}}
; RV64I-NEXT: $x10 = COPY $x11
; RV64I-NEXT: PseudoRET implicit $x10
$x10 = COPY $x11
PseudoRET implicit $x10
...
---
name: virt_to_virt
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0.entry:
; RV64I-LABEL: name: virt_to_virt
; RV64I: PseudoRET
%0:gprb(s64) = G_CONSTANT i64 1
%1:gprb(s64) = COPY %0(s64)
PseudoRET
...
---
name: phys_to_virt
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0.entry:
liveins: $x10
; RV64I-LABEL: name: phys_to_virt
; RV64I: liveins: $x10
; RV64I-NEXT: {{ $}}
; RV64I-NEXT: PseudoRET
%0:gprb(s64) = COPY $x10
PseudoRET
...
|
