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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=riscv32 -mattr=+d -run-pass=instruction-select \
# RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s
---
name: fp_select_s32
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0.entry:
liveins: $x10, $f10_f, $f11_f
; CHECK-LABEL: name: fp_select_s32
; CHECK: liveins: $x10, $f10_f, $f11_f
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $f10_f
; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr32 = COPY $f11_f
; CHECK-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY]], 1
; CHECK-NEXT: [[Select_FPR32_Using_CC_GPR:%[0-9]+]]:fpr32 = Select_FPR32_Using_CC_GPR [[ANDI]], $x0, 1, [[COPY1]], [[COPY2]]
; CHECK-NEXT: $f10_f = COPY [[Select_FPR32_Using_CC_GPR]]
; CHECK-NEXT: PseudoRET implicit $f10_f
%0:gprb(s32) = COPY $x10
%1:fprb(s32) = COPY $f10_f
%2:fprb(s32) = COPY $f11_f
%3:gprb(s32) = G_CONSTANT i32 1
%4:gprb(s32) = G_AND %0, %3
%5:fprb(s32) = G_SELECT %4(s32), %1, %2
$f10_f = COPY %5(s32)
PseudoRET implicit $f10_f
...
---
name: fp_select_s64
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0.entry:
liveins: $x10, $f10_d, $f11_d
; CHECK-LABEL: name: fp_select_s64
; CHECK: liveins: $x10, $f10_d, $f11_d
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $f10_d
; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY $f11_d
; CHECK-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY]], 1
; CHECK-NEXT: [[Select_FPR64_Using_CC_GPR:%[0-9]+]]:fpr64 = Select_FPR64_Using_CC_GPR [[ANDI]], $x0, 1, [[COPY1]], [[COPY2]]
; CHECK-NEXT: $f10_d = COPY [[Select_FPR64_Using_CC_GPR]]
; CHECK-NEXT: PseudoRET implicit $f10_d
%0:gprb(s32) = COPY $x10
%1:fprb(s64) = COPY $f10_d
%2:fprb(s64) = COPY $f11_d
%3:gprb(s32) = G_CONSTANT i32 1
%4:gprb(s32) = G_AND %0, %3
%5:fprb(s64) = G_SELECT %4(s32), %1, %2
$f10_d = COPY %5(s64)
PseudoRET implicit $f10_d
...
|
