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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=riscv32 -mattr=+zfh -run-pass=instruction-select \
# RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s
---
name: fptosi_s32_s16
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.1:
liveins: $f10_h
; CHECK-LABEL: name: fptosi_s32_s16
; CHECK: liveins: $f10_h
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h
; CHECK-NEXT: [[FCVT_W_H:%[0-9]+]]:gpr = nofpexcept FCVT_W_H [[COPY]], 1
; CHECK-NEXT: $x10 = COPY [[FCVT_W_H]]
; CHECK-NEXT: PseudoRET implicit $x10
%0:fprb(s16) = COPY $f10_h
%1:gprb(s32) = G_FPTOSI %0(s16)
$x10 = COPY %1(s32)
PseudoRET implicit $x10
...
---
name: fptoui_s32_s16
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.1:
liveins: $f10_h
; CHECK-LABEL: name: fptoui_s32_s16
; CHECK: liveins: $f10_h
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h
; CHECK-NEXT: [[FCVT_WU_H:%[0-9]+]]:gpr = nofpexcept FCVT_WU_H [[COPY]], 1
; CHECK-NEXT: $x10 = COPY [[FCVT_WU_H]]
; CHECK-NEXT: PseudoRET implicit $x10
%0:fprb(s16) = COPY $f10_h
%1:gprb(s32) = G_FPTOUI %0(s16)
$x10 = COPY %1(s32)
PseudoRET implicit $x10
...
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