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<h1 class="topictitle1">Introducing Intel® Threading Building Blocks</h1>
<div>
<div class="section">
<p>Intel® Threading Building Blocks (Intel® TBB) is a
library that supports scalable parallel programming using standard ISO C++
code. It does not require special languages or compilers. It is designed to
promote scalable data parallel programming. Additionally, it fully supports
nested parallelism, so you can build larger parallel components from smaller
parallel components. To use the library, you specify tasks, not threads, and
let the library map tasks onto threads in an efficient manner.
</p>
<p>Many of the library interfaces employ generic
programming, in which interfaces are defined by requirements on types and not
specific types. The C++ Standard Template Library (STL) is an example of
generic programming. Generic programming enables Intel® Threading Building
Blocks to be flexible yet efficient. The generic interfaces enable you to
customize components to your specific needs.
</p>
<p>The net result is that Intel® Threading Building
Blocks enables you to specify parallelism far more conveniently than using raw
threads, and at the same time can improve performance.
</p>
<p>This document is a reference manual. It is
organized for looking up details about syntax and semantics. You should first
read the
<em>Intel® Threading Building Blocks Getting Started Guide</em> and the
<em>Intel® Threading Building Blocks Tutorial</em> to learn how to use
the library effectively. The
<em>Intel® Threading Building Blocks Design Patterns</em> document is
another useful resource.
</p>
<div class="Note"><h3 class="NoteTipHead">
Tip</h3>
<p>Even experienced parallel programmers should read
the
<em>Intel® Threading Building Blocks Tutorial</em> before using this
reference guide because Intel® Threading Building Blocks uses a surprising
recursive model of parallelism and generic algorithms.
</p>
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<p>Optimization Notice
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Intel's compilers may or may not optimize to the same degree for non-Intel
microprocessors for optimizations that are not unique to Intel microprocessors.
These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other
optimizations. Intel does not guarantee the availability, functionality, or
effectiveness of any optimization on microprocessors not manufactured by Intel.
Microprocessor-dependent optimizations in this product are intended for use
with Intel microprocessors. Certain optimizations not specific to Intel
microarchitecture are reserved for Intel microprocessors. Please refer to the
applicable product User and Reference Guides for more information regarding the
specific instruction sets covered by this notice.
<p>Notice revision #20110804
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