1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367
|
/*
* Copyright (c) 2014 Google, Inc
*
* (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Andreas Heppel <aheppel@sysgo.de>
*
* (C) Copyright 2002, 2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <dm.h>
#include <errno.h>
#include <pci.h>
#include <asm/io.h>
const char *pci_class_str(u8 class)
{
switch (class) {
case PCI_CLASS_NOT_DEFINED:
return "Build before PCI Rev2.0";
break;
case PCI_BASE_CLASS_STORAGE:
return "Mass storage controller";
break;
case PCI_BASE_CLASS_NETWORK:
return "Network controller";
break;
case PCI_BASE_CLASS_DISPLAY:
return "Display controller";
break;
case PCI_BASE_CLASS_MULTIMEDIA:
return "Multimedia device";
break;
case PCI_BASE_CLASS_MEMORY:
return "Memory controller";
break;
case PCI_BASE_CLASS_BRIDGE:
return "Bridge device";
break;
case PCI_BASE_CLASS_COMMUNICATION:
return "Simple comm. controller";
break;
case PCI_BASE_CLASS_SYSTEM:
return "Base system peripheral";
break;
case PCI_BASE_CLASS_INPUT:
return "Input device";
break;
case PCI_BASE_CLASS_DOCKING:
return "Docking station";
break;
case PCI_BASE_CLASS_PROCESSOR:
return "Processor";
break;
case PCI_BASE_CLASS_SERIAL:
return "Serial bus controller";
break;
case PCI_BASE_CLASS_INTELLIGENT:
return "Intelligent controller";
break;
case PCI_BASE_CLASS_SATELLITE:
return "Satellite controller";
break;
case PCI_BASE_CLASS_CRYPT:
return "Cryptographic device";
break;
case PCI_BASE_CLASS_SIGNAL_PROCESSING:
return "DSP";
break;
case PCI_CLASS_OTHERS:
return "Does not fit any class";
break;
default:
return "???";
break;
};
}
__weak int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev)
{
/*
* Check if pci device should be skipped in configuration
*/
if (dev == PCI_BDF(hose->first_busno, 0, 0)) {
#if defined(CONFIG_PCI_CONFIG_HOST_BRIDGE) /* don't skip host bridge */
/*
* Only skip configuration if "pciconfighost" is not set
*/
if (getenv("pciconfighost") == NULL)
return 1;
#else
return 1;
#endif
}
return 0;
}
#if !defined(CONFIG_DM_PCI) || defined(CONFIG_DM_PCI_COMPAT)
/* Get a virtual address associated with a BAR region */
void *pci_map_bar(pci_dev_t pdev, int bar, int flags)
{
pci_addr_t pci_bus_addr;
u32 bar_response;
/* read BAR address */
pci_read_config_dword(pdev, bar, &bar_response);
pci_bus_addr = (pci_addr_t)(bar_response & ~0xf);
/*
* Pass "0" as the length argument to pci_bus_to_virt. The arg
* isn't actualy used on any platform because u-boot assumes a static
* linear mapping. In the future, this could read the BAR size
* and pass that as the size if needed.
*/
return pci_bus_to_virt(pdev, pci_bus_addr, flags, 0, MAP_NOCACHE);
}
void pci_write_bar32(struct pci_controller *hose, pci_dev_t dev, int barnum,
u32 addr_and_ctrl)
{
int bar;
bar = PCI_BASE_ADDRESS_0 + barnum * 4;
pci_hose_write_config_dword(hose, dev, bar, addr_and_ctrl);
}
u32 pci_read_bar32(struct pci_controller *hose, pci_dev_t dev, int barnum)
{
u32 addr;
int bar;
bar = PCI_BASE_ADDRESS_0 + barnum * 4;
pci_hose_read_config_dword(hose, dev, bar, &addr);
if (addr & PCI_BASE_ADDRESS_SPACE_IO)
return addr & PCI_BASE_ADDRESS_IO_MASK;
else
return addr & PCI_BASE_ADDRESS_MEM_MASK;
}
int __pci_hose_bus_to_phys(struct pci_controller *hose,
pci_addr_t bus_addr,
unsigned long flags,
unsigned long skip_mask,
phys_addr_t *pa)
{
struct pci_region *res;
int i;
for (i = 0; i < hose->region_count; i++) {
res = &hose->regions[i];
if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0)
continue;
if (res->flags & skip_mask)
continue;
if (bus_addr >= res->bus_start &&
(bus_addr - res->bus_start) < res->size) {
*pa = (bus_addr - res->bus_start + res->phys_start);
return 0;
}
}
return 1;
}
phys_addr_t pci_hose_bus_to_phys(struct pci_controller *hose,
pci_addr_t bus_addr,
unsigned long flags)
{
phys_addr_t phys_addr = 0;
int ret;
if (!hose) {
puts("pci_hose_bus_to_phys: invalid hose\n");
return phys_addr;
}
#ifdef CONFIG_DM_PCI
/* The root controller has the region information */
hose = pci_bus_to_hose(0);
#endif
/*
* if PCI_REGION_MEM is set we do a two pass search with preference
* on matches that don't have PCI_REGION_SYS_MEMORY set
*/
if ((flags & PCI_REGION_TYPE) == PCI_REGION_MEM) {
ret = __pci_hose_bus_to_phys(hose, bus_addr,
flags, PCI_REGION_SYS_MEMORY, &phys_addr);
if (!ret)
return phys_addr;
}
ret = __pci_hose_bus_to_phys(hose, bus_addr, flags, 0, &phys_addr);
if (ret)
puts("pci_hose_bus_to_phys: invalid physical address\n");
return phys_addr;
}
int __pci_hose_phys_to_bus(struct pci_controller *hose,
phys_addr_t phys_addr,
unsigned long flags,
unsigned long skip_mask,
pci_addr_t *ba)
{
struct pci_region *res;
pci_addr_t bus_addr;
int i;
for (i = 0; i < hose->region_count; i++) {
res = &hose->regions[i];
if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0)
continue;
if (res->flags & skip_mask)
continue;
bus_addr = phys_addr - res->phys_start + res->bus_start;
if (bus_addr >= res->bus_start &&
(bus_addr - res->bus_start) < res->size) {
*ba = bus_addr;
return 0;
}
}
return 1;
}
pci_addr_t pci_hose_phys_to_bus(struct pci_controller *hose,
phys_addr_t phys_addr,
unsigned long flags)
{
pci_addr_t bus_addr = 0;
int ret;
if (!hose) {
puts("pci_hose_phys_to_bus: invalid hose\n");
return bus_addr;
}
#ifdef CONFIG_DM_PCI
/* The root controller has the region information */
hose = pci_bus_to_hose(0);
#endif
/*
* if PCI_REGION_MEM is set we do a two pass search with preference
* on matches that don't have PCI_REGION_SYS_MEMORY set
*/
if ((flags & PCI_REGION_TYPE) == PCI_REGION_MEM) {
ret = __pci_hose_phys_to_bus(hose, phys_addr,
flags, PCI_REGION_SYS_MEMORY, &bus_addr);
if (!ret)
return bus_addr;
}
ret = __pci_hose_phys_to_bus(hose, phys_addr, flags, 0, &bus_addr);
if (ret)
puts("pci_hose_phys_to_bus: invalid physical address\n");
return bus_addr;
}
pci_dev_t pci_find_device(unsigned int vendor, unsigned int device, int index)
{
struct pci_device_id ids[2] = { {}, {0, 0} };
ids[0].vendor = vendor;
ids[0].device = device;
return pci_find_devices(ids, index);
}
pci_dev_t pci_hose_find_devices(struct pci_controller *hose, int busnum,
struct pci_device_id *ids, int *indexp)
{
int found_multi = 0;
u16 vendor, device;
u8 header_type;
pci_dev_t bdf;
int i;
for (bdf = PCI_BDF(busnum, 0, 0);
bdf < PCI_BDF(busnum + 1, 0, 0);
bdf += PCI_BDF(0, 0, 1)) {
if (pci_skip_dev(hose, bdf))
continue;
if (!PCI_FUNC(bdf)) {
pci_read_config_byte(bdf, PCI_HEADER_TYPE,
&header_type);
found_multi = header_type & 0x80;
} else {
if (!found_multi)
continue;
}
pci_read_config_word(bdf, PCI_VENDOR_ID, &vendor);
pci_read_config_word(bdf, PCI_DEVICE_ID, &device);
for (i = 0; ids[i].vendor != 0; i++) {
if (vendor == ids[i].vendor &&
device == ids[i].device) {
if ((*indexp) <= 0)
return bdf;
(*indexp)--;
}
}
}
return -1;
}
pci_dev_t pci_find_class(uint find_class, int index)
{
int bus;
int devnum;
pci_dev_t bdf;
uint32_t class;
for (bus = 0; bus <= pci_last_busno(); bus++) {
for (devnum = 0; devnum < PCI_MAX_PCI_DEVICES - 1; devnum++) {
pci_read_config_dword(PCI_BDF(bus, devnum, 0),
PCI_CLASS_REVISION, &class);
if (class >> 16 == 0xffff)
continue;
for (bdf = PCI_BDF(bus, devnum, 0);
bdf <= PCI_BDF(bus, devnum,
PCI_MAX_PCI_FUNCTIONS - 1);
bdf += PCI_BDF(0, 0, 1)) {
pci_read_config_dword(bdf, PCI_CLASS_REVISION,
&class);
class >>= 8;
if (class != find_class)
continue;
/*
* Decrement the index. We want to return the
* correct device, so index is 0 for the first
* matching device, 1 for the second, etc.
*/
if (index) {
index--;
continue;
}
/* Return index'th controller. */
return bdf;
}
}
}
return -ENODEV;
}
#endif /* !CONFIG_DM_PCI || CONFIG_DM_PCI_COMPAT */
|