1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203
|
/*
* (C) Copyright 2011
* eInfochips Ltd. <www.einfochips.com>
* Written-by: Ajay Bhargav <ajay.bhargav@einfochips.com>
*
* (C) Copyright 2009
* Marvell Semiconductor <www.marvell.com>
* Based on SSP driver
* Written-by: Lei Wen <leiwen@marvell.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <malloc.h>
#include <spi.h>
#include <asm/io.h>
#include <asm/arch/spi.h>
#include <asm/gpio.h>
#define to_armd_spi_slave(s) container_of(s, struct armd_spi_slave, slave)
struct armd_spi_slave {
struct spi_slave slave;
struct ssp_reg *spi_reg;
u32 cr0, cr1;
u32 int_cr1;
u32 clear_sr;
const void *tx;
void *rx;
int gpio_cs_inverted;
};
static int spi_armd_write(struct armd_spi_slave *pss)
{
int wait_timeout = SSP_FLUSH_NUM;
while (--wait_timeout && !(readl(&pss->spi_reg->sssr) & SSSR_TNF))
;
if (!wait_timeout) {
debug("%s: timeout error\n", __func__);
return -1;
}
if (pss->tx != NULL) {
writel(*(u8 *)pss->tx, &pss->spi_reg->ssdr);
++pss->tx;
} else {
writel(0, &pss->spi_reg->ssdr);
}
return 0;
}
static int spi_armd_read(struct armd_spi_slave *pss)
{
int wait_timeout = SSP_FLUSH_NUM;
while (--wait_timeout && !(readl(&pss->spi_reg->sssr) & SSSR_RNE))
;
if (!wait_timeout) {
debug("%s: timeout error\n", __func__);
return -1;
}
if (pss->rx != NULL) {
*(u8 *)pss->rx = readl(&pss->spi_reg->ssdr);
++pss->rx;
} else {
readl(&pss->spi_reg->ssdr);
}
return 0;
}
static int spi_armd_flush(struct armd_spi_slave *pss)
{
unsigned long limit = SSP_FLUSH_NUM;
do {
while (readl(&pss->spi_reg->sssr) & SSSR_RNE)
readl(&pss->spi_reg->ssdr);
} while ((readl(&pss->spi_reg->sssr) & SSSR_BSY) && limit--);
writel(SSSR_ROR, &pss->spi_reg->sssr);
return limit;
}
void spi_cs_activate(struct spi_slave *slave)
{
struct armd_spi_slave *pss = to_armd_spi_slave(slave);
gpio_set_value(slave->cs, pss->gpio_cs_inverted);
}
void spi_cs_deactivate(struct spi_slave *slave)
{
struct armd_spi_slave *pss = to_armd_spi_slave(slave);
gpio_set_value(slave->cs, !pss->gpio_cs_inverted);
}
struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
unsigned int max_hz, unsigned int mode)
{
struct armd_spi_slave *pss;
pss = spi_alloc_slave(struct armd_spi_slave, bus, cs);
if (!pss)
return NULL;
pss->spi_reg = (struct ssp_reg *)SSP_REG_BASE(CONFIG_SYS_SSP_PORT);
pss->cr0 = SSCR0_MOTO | SSCR0_DATASIZE(DEFAULT_WORD_LEN) | SSCR0_SSE;
pss->cr1 = (SSCR1_RXTRESH(RX_THRESH_DEF) & SSCR1_RFT) |
(SSCR1_TXTRESH(TX_THRESH_DEF) & SSCR1_TFT);
pss->cr1 &= ~(SSCR1_SPO | SSCR1_SPH);
pss->cr1 |= (((mode & SPI_CPHA) != 0) ? SSCR1_SPH : 0)
| (((mode & SPI_CPOL) != 0) ? SSCR1_SPO : 0);
pss->int_cr1 = SSCR1_TIE | SSCR1_RIE | SSCR1_TINTE;
pss->clear_sr = SSSR_ROR | SSSR_TINT;
pss->gpio_cs_inverted = mode & SPI_CS_HIGH;
gpio_set_value(cs, !pss->gpio_cs_inverted);
return &pss->slave;
}
void spi_free_slave(struct spi_slave *slave)
{
struct armd_spi_slave *pss = to_armd_spi_slave(slave);
free(pss);
}
int spi_claim_bus(struct spi_slave *slave)
{
struct armd_spi_slave *pss = to_armd_spi_slave(slave);
debug("%s: bus:%i cs:%i\n", __func__, slave->bus, slave->cs);
if (spi_armd_flush(pss) == 0)
return -1;
return 0;
}
void spi_release_bus(struct spi_slave *slave)
{
}
int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
void *din, unsigned long flags)
{
struct armd_spi_slave *pss = to_armd_spi_slave(slave);
uint bytes = bitlen / 8;
unsigned long limit;
int ret = 0;
if (bitlen == 0)
goto done;
/* we can only do 8 bit transfers */
if (bitlen % 8) {
flags |= SPI_XFER_END;
goto done;
}
pss->tx = dout;
pss->rx = din;
if (flags & SPI_XFER_BEGIN) {
spi_cs_activate(slave);
writel(pss->cr1 | pss->int_cr1, &pss->spi_reg->sscr1);
writel(TIMEOUT_DEF, &pss->spi_reg->ssto);
writel(pss->cr0, &pss->spi_reg->sscr0);
}
while (bytes--) {
limit = SSP_FLUSH_NUM;
ret = spi_armd_write(pss);
if (ret)
break;
while ((readl(&pss->spi_reg->sssr) & SSSR_BSY) && limit--)
udelay(1);
ret = spi_armd_read(pss);
if (ret)
break;
}
done:
if (flags & SPI_XFER_END) {
/* Stop SSP */
writel(pss->clear_sr, &pss->spi_reg->sssr);
clrbits_le32(&pss->spi_reg->sscr1, pss->int_cr1);
writel(0, &pss->spi_reg->ssto);
spi_cs_deactivate(slave);
}
return ret;
}
|