File: ram32_2sum.v

package info (click to toggle)
uhd 3.13.1.0-3
  • links: PTS, VCS
  • area: main
  • in suites: buster
  • size: 207,120 kB
  • sloc: cpp: 167,245; ansic: 86,841; vhdl: 53,420; python: 40,839; xml: 13,167; tcl: 5,688; makefile: 2,167; sh: 1,719; pascal: 230; csh: 94; asm: 20; perl: 11
file content (22 lines) | stat: -rw-r--r-- 506 bytes parent folder | download | duplicates (11)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22


module ram32_2sum (input clock, input write, 
		   input [4:0] wr_addr, input [15:0] wr_data,
		   input [4:0] rd_addr1, input [4:0] rd_addr2,
		   output reg [15:0] sum);
   
   reg [15:0] 			ram_array [0:31];
   wire [16:0] 			sum_int;
   
   always @(posedge clock)
     if(write)
       ram_array[wr_addr] <= #1 wr_data;

   assign sum_int = ram_array[rd_addr1] + ram_array[rd_addr2];

   always @(posedge clock)
     sum <= #1 sum_int[16:1] + (sum_int[16]&sum_int[0]);

   
endmodule // ram32_2sum