File: ext_fifo_tb.cmd

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/opt/Xilinx/12.1/ISE_DS/ISE/verilog/src/glbl.v
-y .
-y ../coregen/
-y ../fifo
-y ../models
-y /home/ianb/usrp-fpga/usrp2/sdr_lib
-y /home/ianb/usrp-fpga/usrp2/control_lib
-y /home/ianb/usrp-fpga/usrp2/models
-y /opt/Xilinx/12.1/ISE_DS/ISE/verilog/src/unisims
-y /opt/Xilinx/12.1/ISE_DS/ISE/verilog/src
-y /opt/Xilinx/12.1/ISE_DS/ISE/verilog/src/XilinxCoreLib