File: b200_clk_gen.ucf

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# file: b200_clk_gen.ucf
# 
# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
# 
# This file contains confidential and proprietary information
# of Xilinx, Inc. and is protected under U.S. and
# international copyright and other intellectual property
# laws.
# 
# DISCLAIMER
# This disclaimer is not a license and does not grant any
# rights to the materials distributed herewith. Except as
# otherwise provided in a valid license issued to you by
# Xilinx, and to the maximum extent permitted by applicable
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
# (2) Xilinx shall not be liable (whether in contract or tort,
# including negligence, or under any other theory of
# liability) for any loss or damage of any kind or nature
# related to, arising under or in connection with these
# materials, including for any direct, or any indirect,
# special, incidental, or consequential loss or damage
# (including loss of data, profits, goodwill, or any type of
# loss or damage suffered as a result of any action brought
# by a third party) even if such damage or loss was
# reasonably foreseeable or Xilinx had been advised of the
# possibility of the same.
# 
# CRITICAL APPLICATIONS
# Xilinx products are not designed or intended to be fail-
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# 
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
# PART OF THIS FILE AT ALL TIMES.
# 

# Input clock periods. These duplicate the values entered for the
#  input clocks. You can use these to time your system
#----------------------------------------------------------------
# Differential clock only needs one constraint
NET "CLK_IN1_P" TNM_NET = "CLK_IN1_P";
TIMESPEC "TS_CLK_IN1_P" = PERIOD "CLK_IN1_P" 25.0 ns HIGH 50% INPUT_JITTER 250.0ps;

# Derived clock periods. These are commented out because they are 
#   automatically propogated by the tools
# However, if you'd like to use them for module level testing, you 
#   can copy them into your module level timing checks
#-----------------------------------------------------------------
# NET "clk_int[1]" TNM_NET = "CLK_OUT1";
# TIMESPEC "TS_CLK_OUT1" = PERIOD "CLK_OUT1" 40.000 MHz;

# NET "clk_int[2]" TNM_NET = "CLK_OUT2";
# TIMESPEC "TS_CLK_OUT2" = PERIOD "CLK_OUT2" 100.000 MHz;
# NET "clk_int[3]" TNM_NET = "CLK_OUT3";
# TIMESPEC "TS_CLK_OUT3" = PERIOD "CLK_OUT3" 100.000 MHz;

# FALSE PATH constraints 
PIN "RESET" TIG;