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/*******************************************************************************
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* of Xilinx, Inc. and is protected under U.S. and *
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// Generated from component ID: xilinx.com:ip:fir_compiler:5.0
// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
hbdec2 YourInstanceName (
.sclr(sclr), // input sclr
.clk(clk), // input clk
.ce(ce), // input ce
.nd(nd), // input nd
.coef_ld(coef_ld), // input coef_ld
.coef_we(coef_we), // input coef_we
.coef_din(coef_din), // input [17 : 0] coef_din
.rfd(rfd), // output rfd
.rdy(rdy), // output rdy
.data_valid(data_valid), // output data_valid
.din_1(din_1), // input [23 : 0] din_1
.din_2(din_2), // input [23 : 0] din_2
.dout_1(dout_1), // output [46 : 0] dout_1
.dout_2(dout_2)); // output [46 : 0] dout_2
// INST_TAG_END ------ End INSTANTIATION Template ---------
// You must compile the wrapper file hbdec2.v when simulating
// the core, hbdec2. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
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