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##############################################################
#
# Xilinx Core Generator version 14.7
# Date: Thu Jan 15 00:59:52 2015
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# Generated from component: xilinx.com:ip:fir_compiler:6.3
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = Verilog
SET device = xc7k325t
SET devicefamily = kintex7
SET flowvendor = Other
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = ffg900
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -2
SET verilogsim = true
SET vhdlsim = false
# END Project Options
# BEGIN Select
SELECT FIR_Compiler xilinx.com:ip:fir_compiler:6.3
# END Select
# BEGIN Parameters
CSET bestprecision=false
CSET channel_sequence=Basic
CSET clock_frequency=200
CSET coefficient_buffer_type=Automatic
CSET coefficient_file=./decim_4_5.coe
CSET coefficient_fractional_bits=0
CSET coefficient_reload=true
CSET coefficient_sets=1
CSET coefficient_sign=Signed
CSET coefficient_structure=Non_Symmetric
CSET coefficient_width=25
CSET coefficientsource=COE_File
CSET coefficientvector=6,0,-4,-3,5,6,-6,-13,7,44,64,44,7,-13,-6,6,5,-3,-4,0,6
CSET columnconfig=41
CSET component_name=simple_fir
CSET data_buffer_type=Automatic
CSET data_fractional_bits=0
CSET data_has_tlast=Packet_Framing
CSET data_sign=Signed
CSET data_tuser_width=1
CSET data_width=16
CSET decimation_rate=1
CSET displayreloadorder=false
CSET filter_architecture=Systolic_Multiply_Accumulate
CSET filter_selection=1
CSET filter_type=Single_Rate
CSET gen_mif_files=false
CSET gen_mif_from_coe=false
CSET gen_mif_from_spec=false
CSET gui_behaviour=Coregen
CSET hardwareoversamplingrate=1
CSET has_aclken=false
CSET has_aresetn=true
CSET input_buffer_type=Automatic
CSET inter_column_pipe_length=4
CSET interpolation_rate=1
CSET m_data_has_tready=true
CSET m_data_has_tuser=Not_Required
CSET multi_column_support=Automatic
CSET num_reload_slots=1
CSET number_channels=1
CSET number_paths=2
CSET optimization_goal=Area
CSET output_buffer_type=Automatic
CSET output_rounding_mode=Full_Precision
CSET output_width=47
CSET passband_max=0.5
CSET passband_min=0.0
CSET pattern_list=P4-0,P4-1,P4-2,P4-3,P4-4
CSET preference_for_other_storage=Automatic
CSET quantization=Integer_Coefficients
CSET rate_change_type=Integer
CSET ratespecification=Frequency_Specification
CSET reload_file=no_coe_file_loaded
CSET reset_data_vector=false
CSET s_config_method=Single
CSET s_config_sync_mode=On_Packet
CSET s_data_has_fifo=true
CSET s_data_has_tuser=Not_Required
CSET sample_frequency=200
CSET sampleperiod=1
CSET select_pattern=All
CSET stopband_max=1.0
CSET stopband_min=0.5
CSET zero_pack_factor=1
# END Parameters
# BEGIN Extra information
MISC pkg_timestamp=2013-07-22T10:45:45Z
# END Extra information
GENERATE
# CRC: 95586a8e
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