1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178
|
//
// Copyright 2018 Ettus Research, A National Instruments Company
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
// Module: axis_ingress_vc_buff
// Description:
// A wrapper around a buffer to implement one or more virtual channels
// Supports gate a packet for cut-through routing
module axis_ingress_vc_buff #(
parameter WIDTH = 64, // Width of the datapath
parameter NUM_VCS = 2, // Number of virtual channels
parameter SIZE = 5, // Virtual channel buffer size
parameter ROUTING = "WORMHOLE", // Routing (switching) method {WORMHOLE, CUT-THROUGH}
parameter DEST_W = (NUM_VCS > 1) ? $clog2(NUM_VCS) : 1 // PRIVATE
) (
input wire clk,
input wire reset,
input wire [WIDTH-1:0] s_axis_tdata,
input wire [DEST_W-1:0] s_axis_tdest,
input wire s_axis_tlast,
input wire s_axis_tvalid,
output wire s_axis_tready,
output wire [WIDTH-1:0] m_axis_tdata,
output wire m_axis_tlast,
output wire m_axis_tvalid,
input wire m_axis_tready
);
generate if (NUM_VCS > 1) begin
//----------------------------------------------------
// Multiple virtual channels
//----------------------------------------------------
wire [(WIDTH*NUM_VCS)-1:0] bufin_tdata , bufout_tdata ;
wire [NUM_VCS-1:0] bufin_tlast , bufout_tlast ;
wire [NUM_VCS-1:0] bufin_tvalid, bufout_tvalid;
wire [NUM_VCS-1:0] bufin_tready, bufout_tready;
axi_demux #(
.WIDTH(WIDTH), .SIZE(NUM_VCS),
.PRE_FIFO_SIZE(0 /* must be 0 */), .POST_FIFO_SIZE(0)
) vc_demux_i (
.clk (clk),
.reset (reset),
.clear (1'b0),
.header (/* unused */),
.dest (s_axis_tdest ),
.i_tdata (s_axis_tdata ),
.i_tlast (s_axis_tlast ),
.i_tvalid (s_axis_tvalid),
.i_tready (s_axis_tready),
.o_tdata (bufin_tdata),
.o_tlast (bufin_tlast),
.o_tvalid (bufin_tvalid),
.o_tready (bufin_tready)
);
genvar vc;
for (vc = 0; vc < NUM_VCS; vc = vc + 1) begin
if (ROUTING == "WORMHOLE") begin
axi_fifo #(
.WIDTH(WIDTH+1), .SIZE(SIZE)
) buf_i (
.clk (clk),
.reset (reset),
.clear (1'b0),
.i_tdata ({bufin_tlast[vc], bufin_tdata [(vc*WIDTH)+:WIDTH]}),
.i_tvalid (bufin_tvalid [vc]),
.i_tready (bufin_tready [vc]),
.o_tdata ({bufout_tlast[vc], bufout_tdata [(vc*WIDTH)+:WIDTH]}),
.o_tvalid (bufout_tvalid[vc]),
.o_tready (bufout_tready[vc]),
.space (),
.occupied ()
);
end else begin
axi_packet_gate #(
.WIDTH(WIDTH), .SIZE(SIZE)
) buf_i (
.clk (clk),
.reset (reset),
.clear (1'b0),
.i_tdata (bufin_tdata[(vc*WIDTH)+:WIDTH]),
.i_tlast (bufin_tlast[vc]),
.i_tvalid (bufin_tvalid[vc]),
.i_tready (bufin_tready[vc]),
.i_terror (1'b0),
.o_tdata (bufout_tdata[(vc*WIDTH)+:WIDTH]),
.o_tlast (bufout_tlast[vc]),
.o_tvalid (bufout_tvalid[vc]),
.o_tready (bufout_tready[vc])
);
end
end
axi_mux #(
.WIDTH(WIDTH), .SIZE(NUM_VCS),
.PRE_FIFO_SIZE(0), .POST_FIFO_SIZE(1)
) vc_mux_i (
.clk (clk),
.reset (reset),
.clear (1'b0),
.i_tdata (bufout_tdata ),
.i_tlast (bufout_tlast ),
.i_tvalid (bufout_tvalid),
.i_tready (bufout_tready),
.o_tdata (m_axis_tdata ),
.o_tlast (m_axis_tlast ),
.o_tvalid (m_axis_tvalid),
.o_tready (m_axis_tready)
);
end else begin
//----------------------------------------------------
// Single virtual channel
//----------------------------------------------------
wire [WIDTH-1:0] pipe_tdata;
wire pipe_tlast;
wire pipe_tvalid;
wire pipe_tready;
if (ROUTING == "WORMHOLE") begin
axi_fifo #(
.WIDTH(WIDTH+1), .SIZE(SIZE)
) buf_i (
.clk (clk),
.reset (reset),
.clear (1'b0),
.i_tdata ({s_axis_tlast, s_axis_tdata}),
.i_tvalid (s_axis_tvalid ),
.i_tready (s_axis_tready ),
.o_tdata ({pipe_tlast, pipe_tdata}),
.o_tvalid (pipe_tvalid),
.o_tready (pipe_tready),
.space (),
.occupied ()
);
end else begin
axi_packet_gate #(
.WIDTH(WIDTH), .SIZE(SIZE)
) buf_i (
.clk (clk),
.reset (reset),
.clear (1'b0),
.i_tdata (s_axis_tdata),
.i_tlast (s_axis_tlast),
.i_tvalid (s_axis_tvalid),
.i_tready (s_axis_tready),
.i_terror (1'b0),
.o_tdata (pipe_tdata),
.o_tlast (pipe_tlast),
.o_tvalid (pipe_tvalid),
.o_tready (pipe_tready)
);
end
axi_fifo #(
.WIDTH(WIDTH+1), .SIZE(1)
) buf_i (
.clk (clk),
.reset (reset),
.clear (1'b0),
.i_tdata ({pipe_tlast, pipe_tdata}),
.i_tvalid (pipe_tvalid ),
.i_tready (pipe_tready ),
.o_tdata ({m_axis_tlast, m_axis_tdata}),
.o_tvalid (m_axis_tvalid),
.o_tready (m_axis_tready),
.space (),
.occupied ()
);
end endgenerate
endmodule
|