File: run_iverilog

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iverilog -y . \
-D SIM_SCRIPT=true \
../../../vita/new_tx_tb.v \
-y ../../../vita/ \
-y ../../../fifo/ \
-y /opt/Xilinx/14.4/ISE_DS/ISE/verilog/src/unisims/ \
-y ../../../control/ \
-y ../../../timing/ \
-y ../../../dsp/  \
/opt/Xilinx/14.4/ISE_DS/ISE/verilog/src/ \
-y ../../../../../usrp2/models/ \
-Wall \
-o new_tx_tb.exe

./new_tx_tb.exe