File: run_isim

package info (click to toggle)
uhd 3.15.0.0-4
  • links: PTS, VCS
  • area: main
  • in suites: bullseye
  • size: 202,252 kB
  • sloc: cpp: 182,756; ansic: 94,109; vhdl: 53,420; python: 45,849; xml: 12,956; tcl: 7,046; makefile: 2,248; sh: 1,741; pascal: 230; javascript: 120; csh: 94; asm: 20; perl: 11
file content (22 lines) | stat: -rwxr-xr-x 892 bytes parent folder | download | duplicates (7)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
vlogcomp -work work ${XILINX}/verilog/src/glbl.v

# usrp3/top/b200/sim/sim_b200_io/siso 
vlogcomp  -work work --sourcelibext .v \
        --sourcelibdir ../../../../../lib/axi \
        --sourcelibdir ../../../../../lib/fifo \
        --sourcelibdir ../../../../../lib/control \
        --sourcelibdir ../../../coregen \
        --sourcelibdir ../../../ \
        --sourcelibdir ../../../../../lib/timing \
        --sourcelibdir ../../../../../lib/vita \
        --sourcelibdir ../../../../../lib/packet_proc \
        --sourcelibdir ../../../../../lib/dsp \
        --sourcelibdir ../../../../../lib/wishbone \
        --sourcelibdir ../../../../../lib/gpif2 \
	--sourcelibdir ../../../../../lib/io \
        ../../b200_io_tb.v

fuse work.b200_io_tb work.glbl  -L unisims_ver -L xilinxcorelib_ver -o b200_io_tb.exe

# run the simulation scrip
./b200_io_tb.exe   -gui #-tclbatch simcmds.tcl