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///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2015 Xilinx, Inc.
// All Rights Reserved
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 14.6
// \ \ Application: Xilinx CORE Generator
// / / Filename : chipscope_icon.veo
// /___/ /\ Timestamp : Tue Apr 14 17:06:06 PDT 2015
// \ \ / \
// \___\/\___\
//
// Design Name: ISE Instantiation template
///////////////////////////////////////////////////////////////////////////////
// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
chipscope_icon YourInstanceName (
.CONTROL0(CONTROL0) // INOUT BUS [35:0]
);
// INST_TAG_END ------ End INSTANTIATION Template ---------
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