1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
|
// SPDX-License-Identifier: GPL-2.0 OR X11
/*
* Copyright (c) 2018 National Instruments Corp
*/
&fpga_full {
uio@40010000 {
compatible = "usrp-uio";
reg = <0x40010000 0x1000>;
reg-names = "mboard-regs";
status = "okay";
};
crossbar@40011000 {
compatible = "ni,platform-crossbar-rp";
reg = <0x40011000 0x1000>;
status = "okay";
rfnoc,ports = <0x10>;
clocks = <&clkc 15>;
clock-names = "bus_clk";
};
uio@40014000 {
compatible = "usrp-uio";
reg = <0x40014000 0x4000>;
reg-names = "dboard-regs";
status = "okay";
};
};
&spi0 {
status = "okay";
cs-gpios = <0>, <0>, <0>, <&gpio0 62 0>;
spidev0: spidev@0 {
compatible = "rohm,dh2228fv";
reg = <0>;
status = "okay";
spi-max-frequency = <1000000>;
};
};
&spi1 {
status = "okay";
cs-gpios = <0>, <0>, <0>, <&gpio0 63 0>;
spidev1: spidev@0 {
compatible = "rohm,dh2228fv";
reg = <0>;
status = "okay";
spi-max-frequency = <1000000>;
};
};
|
