File: coregen.cgp

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# Date: Fri Oct 15 07:50:19 2010

SET addpads = false
SET asysymbol = false
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = Verilog
SET device = xc3s2000
SET devicefamily = spartan3
SET flowvendor = Other
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = fg456
SET removerpms = false
SET simulationfiles = Structural
SET speedgrade = -5
SET verilogsim = true
SET vhdlsim = false
SET workingdirectory = /tmp/

# CRC: 983b9b45